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SoCFPGA updates for v4.2
- Add big endian support - Add earlyprintk support on UART1 that is used on Arria10 - Remove the need to map uart_io_desc - Use of_iomap to map the SCU - Remove socfpga_smp_init_cpus as arm_dt_init_cpu_maps is already doing the CPU mapping. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) iQIcBAABAgAGBQJVU1X6AAoJEBmUBAuBoyj0ixoP/3l2MxAxQt+SRz70y3ceFqx+ IVbGpcDQdm7RohCFQVV7PVtpjm+RllYjjlRYWN/5/xfUEgjUgCiYlEPch+zFBDvA u9jpK7EdXHUYjAYmlti+Rw4jXXsYy+DzkZeMm6t/MlSj61exKW9iRU+/cdhXDyLx m81fGf+M8V/2xMIbHC6f/6xk2+a8WtTwCoh1FaCJLp+qkedQ4QOJPDjYSWBiubXH g7ydcuIiBpOuc57E1rzFWHeJgQu9VO+hLrNrazrfN/awbonPEL7hMJR2+odrDzHw wnwijqQCRDW1dZOAKNulH7h/9IzxjFyyIjdAbUF8ZplxIT0vtLbYPldd/435XJFX 9VCUzVfAc0Vu5sfl3InbcRNoJDkCPavqcug1pYJkJlE8TeHcV8ylC7uzhWWrIRWa mzJq+j3p/E2pbvfv9YHccNaGRL4p9icN0eojM3fSwAlG9rAsDGFGNJH3Qb4tuwem H3MyhrIr9eveVBSkvz71sPy+ZHRL7EcPVFggpyXG2kNptb/K1P6cdDBO+mfl7ymM oVaKaGfpm3sCF9h/vLDWlsZUVF9eEsWO4qx5b0852T94WPkG+qg8p+MCYX2/7lGO 41nKAWZpKRQj/9LvQpxlPnZSUhqcOPuHVVgMCDaXbwN9tGo7hJuaHpq4abElH3Ha h1lu5YGA9V0wf+zbK3S/ =60ig -----END PGP SIGNATURE----- Merge tag 'socfpga_updates_for_v4.2' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into next/soc Merge "SoCFPGA updates for v4.2" from Dinh Nguyen: - Add big endian support - Add earlyprintk support on UART1 that is used on Arria10 - Remove the need to map uart_io_desc - Use of_iomap to map the SCU - Remove socfpga_smp_init_cpus as arm_dt_init_cpu_maps is already doing the CPU mapping. * tag 'socfpga_updates_for_v4.2' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux: ARM: socfpga: use of_iomap to map the SCU ARM: socfpga: remove the need to map uart_io_desc ARM: socfpga: Add support for UART1 debug uart for earlyprintk ARM: socfpga: support big endian for socfpga ARM: socfpga: enable big endian for secondary core(s) ARM: debug: fix big endian operation for 8250 word mode
This commit is contained in:
commit
94db5b98d0
7 changed files with 39 additions and 68 deletions
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@ -908,13 +908,22 @@ choice
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on SA-11x0 UART ports. The kernel will check for the first
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enabled UART in a sequence 3-1-2.
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config DEBUG_SOCFPGA_UART
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config DEBUG_SOCFPGA_UART0
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depends on ARCH_SOCFPGA
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bool "Use SOCFPGA UART for low-level debug"
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bool "Use SOCFPGA UART0 for low-level debug"
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select DEBUG_UART_8250
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help
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Say Y here if you want kernel low-level debugging support
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on SOCFPGA based platforms.
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on SOCFPGA(Cyclone 5 and Arria 5) based platforms.
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config DEBUG_SOCFPGA_UART1
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depends on ARCH_SOCFPGA
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bool "Use SOCFPGA UART1 for low-level debug"
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select DEBUG_UART_8250
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help
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Say Y here if you want kernel low-level debugging support
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on SOCFPGA(Arria 10) based platforms.
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config DEBUG_SUN9I_UART0
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bool "Kernel low-level debugging messages via sun9i UART0"
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@ -1407,7 +1416,8 @@ config DEBUG_UART_PHYS
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default 0xfd883000 if DEBUG_ALPINE_UART0
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default 0xfe800000 if ARCH_IOP32X
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default 0xff690000 if DEBUG_RK32_UART2
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default 0xffc02000 if DEBUG_SOCFPGA_UART
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default 0xffc02000 if DEBUG_SOCFPGA_UART0
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default 0xffc02100 if DEBUG_SOCFPGA_UART1
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default 0xffd82340 if ARCH_IOP13XX
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default 0xffe40000 if DEBUG_RCAR_GEN1_SCIF0
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default 0xffe42000 if DEBUG_RCAR_GEN1_SCIF2
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@ -1485,7 +1495,8 @@ config DEBUG_UART_VIRT
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default 0xfeb26000 if DEBUG_RK3X_UART1
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default 0xfeb30c00 if DEBUG_KEYSTONE_UART0
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default 0xfeb31000 if DEBUG_KEYSTONE_UART1
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default 0xfec02000 if DEBUG_SOCFPGA_UART
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default 0xfec02000 if DEBUG_SOCFPGA_UART0
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default 0xfec02100 if DEBUG_SOCFPGA_UART1
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default 0xfec12000 if DEBUG_MVEBU_UART0 || DEBUG_MVEBU_UART0_ALTERNATE
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default 0xfec12100 if DEBUG_MVEBU_UART1_ALTERNATE
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default 0xfec10000 if DEBUG_SIRFATLAS7_UART0
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@ -1530,8 +1541,9 @@ config DEBUG_UART_8250_WORD
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bool "Use 32-bit accesses for 8250 UART"
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depends on DEBUG_LL_UART_8250 || DEBUG_UART_8250
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depends on DEBUG_UART_8250_SHIFT >= 2
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default y if DEBUG_PICOXCELL_UART || DEBUG_SOCFPGA_UART || \
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ARCH_KEYSTONE || DEBUG_ALPINE_UART0 || \
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default y if DEBUG_PICOXCELL_UART || DEBUG_SOCFPGA_UART0 || \
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DEBUG_SOCFPGA_UART1 || ARCH_KEYSTONE || \
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DEBUG_ALPINE_UART0 || \
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DEBUG_DAVINCI_DMx_UART0 || DEBUG_DAVINCI_DA8XX_UART1 || \
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DEBUG_DAVINCI_DA8XX_UART2 || \
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DEBUG_BCM_KONA_UART || DEBUG_RK32_UART2 || \
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@ -16,11 +16,14 @@
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#ifdef CONFIG_DEBUG_UART_8250_WORD
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.macro store, rd, rx:vararg
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ARM_BE8(rev \rd, \rd)
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str \rd, \rx
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ARM_BE8(rev \rd, \rd)
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.endm
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.macro load, rd, rx:vararg
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ldr \rd, \rx
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ARM_BE8(rev \rd, \rd)
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.endm
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#else
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.macro store, rd, rx:vararg
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@ -1,5 +1,6 @@
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config ARCH_SOCFPGA
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bool "Altera SOCFPGA family" if ARCH_MULTI_V7
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select ARCH_SUPPORTS_BIG_ENDIAN
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select ARM_AMBA
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select ARM_GIC
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select CACHE_L2X0
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@ -32,7 +32,6 @@
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#define RSTMGR_MPUMODRST_CPU1 0x2 /* CPU1 Reset */
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extern void socfpga_secondary_startup(void);
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extern void __iomem *socfpga_scu_base_addr;
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extern void socfpga_init_clocks(void);
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extern void socfpga_sysmgr_init(void);
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@ -10,6 +10,7 @@
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#include <linux/linkage.h>
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#include <linux/init.h>
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#include <asm/memory.h>
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#include <asm/assembler.h>
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.arch armv7-a
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@ -18,12 +19,14 @@ ENTRY(secondary_trampoline)
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* Thus, we can just subtract the PAGE_OFFSET to get the physical
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* address of &cpu1start_addr. This would not work for platforms
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* where the physical memory does not start at 0x0.
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*/
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*/
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ARM_BE8(setend be)
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adr r0, 1f
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ldmia r0, {r1, r2}
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sub r2, r2, #PAGE_OFFSET
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ldr r3, [r2]
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ldr r4, [r3]
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ARM_BE8(rev r4, r4)
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bx r4
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.align
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@ -54,32 +54,20 @@ static int socfpga_boot_secondary(unsigned int cpu, struct task_struct *idle)
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return 0;
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}
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/*
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* Initialise the CPU possible map early - this describes the CPUs
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* which may be present or become present in the system.
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*/
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static void __init socfpga_smp_init_cpus(void)
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{
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unsigned int i, ncores;
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ncores = scu_get_core_count(socfpga_scu_base_addr);
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for (i = 0; i < ncores; i++)
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set_cpu_possible(i, true);
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/* sanity check */
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if (ncores > num_possible_cpus()) {
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pr_warn("socfpga: no. of cores (%d) greater than configured"
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"maximum of %d - clipping\n", ncores, num_possible_cpus());
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ncores = num_possible_cpus();
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}
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for (i = 0; i < ncores; i++)
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set_cpu_possible(i, true);
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}
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static void __init socfpga_smp_prepare_cpus(unsigned int max_cpus)
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{
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struct device_node *np;
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void __iomem *socfpga_scu_base_addr;
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np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu");
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if (!np) {
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pr_err("%s: missing scu\n", __func__);
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return;
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}
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socfpga_scu_base_addr = of_iomap(np, 0);
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if (!socfpga_scu_base_addr)
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return;
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scu_enable(socfpga_scu_base_addr);
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}
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@ -96,7 +84,6 @@ static void socfpga_cpu_die(unsigned int cpu)
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}
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struct smp_operations socfpga_smp_ops __initdata = {
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.smp_init_cpus = socfpga_smp_init_cpus,
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.smp_prepare_cpus = socfpga_smp_prepare_cpus,
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.smp_boot_secondary = socfpga_boot_secondary,
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#ifdef CONFIG_HOTPLUG_CPU
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@ -27,43 +27,10 @@
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#include "core.h"
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void __iomem *socfpga_scu_base_addr = ((void __iomem *)(SOCFPGA_SCU_VIRT_BASE));
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void __iomem *sys_manager_base_addr;
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void __iomem *rst_manager_base_addr;
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unsigned long socfpga_cpu1start_addr;
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static struct map_desc scu_io_desc __initdata = {
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.virtual = SOCFPGA_SCU_VIRT_BASE,
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.pfn = 0, /* run-time */
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.length = SZ_8K,
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.type = MT_DEVICE,
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};
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static struct map_desc uart_io_desc __initdata = {
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.virtual = 0xfec02000,
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.pfn = __phys_to_pfn(0xffc02000),
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.length = SZ_8K,
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.type = MT_DEVICE,
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};
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static void __init socfpga_scu_map_io(void)
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{
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unsigned long base;
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/* Get SCU base */
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asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (base));
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scu_io_desc.pfn = __phys_to_pfn(base);
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iotable_init(&scu_io_desc, 1);
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}
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static void __init socfpga_map_io(void)
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{
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socfpga_scu_map_io();
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iotable_init(&uart_io_desc, 1);
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early_printk("Early printk initialized\n");
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}
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void __init socfpga_sysmgr_init(void)
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{
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struct device_node *np;
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.l2c_aux_val = 0,
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.l2c_aux_mask = ~0,
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.smp = smp_ops(socfpga_smp_ops),
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.map_io = socfpga_map_io,
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.init_irq = socfpga_init_irq,
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.restart = socfpga_cyclone5_restart,
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.dt_compat = altera_dt_match,
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