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SoCFPGA updates for v4.2

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- Add big endian support
 - Add earlyprintk support on UART1 that is used on Arria10
 - Remove the need to map uart_io_desc
 - Use of_iomap to map the SCU
 - Remove socfpga_smp_init_cpus as arm_dt_init_cpu_maps is already doing
   the CPU mapping.
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Merge tag 'socfpga_updates_for_v4.2' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into next/soc

Merge "SoCFPGA updates for v4.2" from Dinh Nguyen:

- Add big endian support
- Add earlyprintk support on UART1 that is used on Arria10
- Remove the need to map uart_io_desc
- Use of_iomap to map the SCU
- Remove socfpga_smp_init_cpus as arm_dt_init_cpu_maps is already doing
  the CPU mapping.

* tag 'socfpga_updates_for_v4.2' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux:
  ARM: socfpga: use of_iomap to map the SCU
  ARM: socfpga: remove the need to map uart_io_desc
  ARM: socfpga: Add support for UART1 debug uart for earlyprintk
  ARM: socfpga: support big endian for socfpga
  ARM: socfpga: enable big endian for secondary core(s)
  ARM: debug: fix big endian operation for 8250 word mode
This commit is contained in:
Arnd Bergmann 2015-05-13 17:49:03 +02:00
commit 94db5b98d0
7 changed files with 39 additions and 68 deletions
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26
arch/arm/Kconfig.debug
View file

@ -908,13 +908,22 @@ choice
on SA-11x0 UART ports. The kernel will check for the first
enabled UART in a sequence 3-1-2.
config DEBUG_SOCFPGA_UART
config DEBUG_SOCFPGA_UART0
depends on ARCH_SOCFPGA
bool "Use SOCFPGA UART for low-level debug"
bool "Use SOCFPGA UART0 for low-level debug"
select DEBUG_UART_8250
help
Say Y here if you want kernel low-level debugging support
on SOCFPGA based platforms.
on SOCFPGA(Cyclone 5 and Arria 5) based platforms.
config DEBUG_SOCFPGA_UART1
depends on ARCH_SOCFPGA
bool "Use SOCFPGA UART1 for low-level debug"
select DEBUG_UART_8250
help
Say Y here if you want kernel low-level debugging support
on SOCFPGA(Arria 10) based platforms.
config DEBUG_SUN9I_UART0
bool "Kernel low-level debugging messages via sun9i UART0"
@ -1407,7 +1416,8 @@ config DEBUG_UART_PHYS
default 0xfd883000 if DEBUG_ALPINE_UART0
default 0xfe800000 if ARCH_IOP32X
default 0xff690000 if DEBUG_RK32_UART2
default 0xffc02000 if DEBUG_SOCFPGA_UART
default 0xffc02000 if DEBUG_SOCFPGA_UART0
default 0xffc02100 if DEBUG_SOCFPGA_UART1
default 0xffd82340 if ARCH_IOP13XX
default 0xffe40000 if DEBUG_RCAR_GEN1_SCIF0
default 0xffe42000 if DEBUG_RCAR_GEN1_SCIF2
@ -1485,7 +1495,8 @@ config DEBUG_UART_VIRT
default 0xfeb26000 if DEBUG_RK3X_UART1
default 0xfeb30c00 if DEBUG_KEYSTONE_UART0
default 0xfeb31000 if DEBUG_KEYSTONE_UART1
default 0xfec02000 if DEBUG_SOCFPGA_UART
default 0xfec02000 if DEBUG_SOCFPGA_UART0
default 0xfec02100 if DEBUG_SOCFPGA_UART1
default 0xfec12000 if DEBUG_MVEBU_UART0 || DEBUG_MVEBU_UART0_ALTERNATE
default 0xfec12100 if DEBUG_MVEBU_UART1_ALTERNATE
default 0xfec10000 if DEBUG_SIRFATLAS7_UART0
@ -1530,8 +1541,9 @@ config DEBUG_UART_8250_WORD
bool "Use 32-bit accesses for 8250 UART"
depends on DEBUG_LL_UART_8250 || DEBUG_UART_8250
depends on DEBUG_UART_8250_SHIFT >= 2
default y if DEBUG_PICOXCELL_UART || DEBUG_SOCFPGA_UART || \
ARCH_KEYSTONE || DEBUG_ALPINE_UART0 || \
default y if DEBUG_PICOXCELL_UART || DEBUG_SOCFPGA_UART0 || \
DEBUG_SOCFPGA_UART1 || ARCH_KEYSTONE || \
DEBUG_ALPINE_UART0 || \
DEBUG_DAVINCI_DMx_UART0 || DEBUG_DAVINCI_DA8XX_UART1 || \
DEBUG_DAVINCI_DA8XX_UART2 || \
DEBUG_BCM_KONA_UART || DEBUG_RK32_UART2 || \

3
arch/arm/include/debug/8250.S
View file

@ -16,11 +16,14 @@
#ifdef CONFIG_DEBUG_UART_8250_WORD
.macro store, rd, rx:vararg
ARM_BE8(rev \rd, \rd)
str \rd, \rx
ARM_BE8(rev \rd, \rd)
.endm
.macro load, rd, rx:vararg
ldr \rd, \rx
ARM_BE8(rev \rd, \rd)
.endm
#else
.macro store, rd, rx:vararg

1
arch/arm/mach-socfpga/Kconfig
View file

@ -1,5 +1,6 @@
config ARCH_SOCFPGA
bool "Altera SOCFPGA family" if ARCH_MULTI_V7
select ARCH_SUPPORTS_BIG_ENDIAN
select ARM_AMBA
select ARM_GIC
select CACHE_L2X0

1
arch/arm/mach-socfpga/core.h
View file

@ -32,7 +32,6 @@
#define RSTMGR_MPUMODRST_CPU1 0x2 /* CPU1 Reset */
extern void socfpga_secondary_startup(void);
extern void __iomem *socfpga_scu_base_addr;
extern void socfpga_init_clocks(void);
extern void socfpga_sysmgr_init(void);

5
arch/arm/mach-socfpga/headsmp.S
View file

@ -10,6 +10,7 @@
#include <linux/linkage.h>
#include <linux/init.h>
#include <asm/memory.h>
#include <asm/assembler.h>
.arch armv7-a
@ -18,12 +19,14 @@ ENTRY(secondary_trampoline)
* Thus, we can just subtract the PAGE_OFFSET to get the physical
* address of &cpu1start_addr. This would not work for platforms
* where the physical memory does not start at 0x0.
*/
*/
ARM_BE8(setend be)
adr r0, 1f
ldmia r0, {r1, r2}
sub r2, r2, #PAGE_OFFSET
ldr r3, [r2]
ldr r4, [r3]
ARM_BE8(rev r4, r4)
bx r4
.align

37
arch/arm/mach-socfpga/platsmp.c
View file

@ -54,32 +54,20 @@ static int socfpga_boot_secondary(unsigned int cpu, struct task_struct *idle)
return 0;
}
/*
* Initialise the CPU possible map early - this describes the CPUs
* which may be present or become present in the system.
*/
static void __init socfpga_smp_init_cpus(void)
{
unsigned int i, ncores;
ncores = scu_get_core_count(socfpga_scu_base_addr);
for (i = 0; i < ncores; i++)
set_cpu_possible(i, true);
/* sanity check */
if (ncores > num_possible_cpus()) {
pr_warn("socfpga: no. of cores (%d) greater than configured"
"maximum of %d - clipping\n", ncores, num_possible_cpus());
ncores = num_possible_cpus();
}
for (i = 0; i < ncores; i++)
set_cpu_possible(i, true);
}
static void __init socfpga_smp_prepare_cpus(unsigned int max_cpus)
{
struct device_node *np;
void __iomem *socfpga_scu_base_addr;
np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu");
if (!np) {
pr_err("%s: missing scu\n", __func__);
return;
}
socfpga_scu_base_addr = of_iomap(np, 0);
if (!socfpga_scu_base_addr)
return;
scu_enable(socfpga_scu_base_addr);
}
@ -96,7 +84,6 @@ static void socfpga_cpu_die(unsigned int cpu)
}
struct smp_operations socfpga_smp_ops __initdata = {
.smp_init_cpus = socfpga_smp_init_cpus,
.smp_prepare_cpus = socfpga_smp_prepare_cpus,
.smp_boot_secondary = socfpga_boot_secondary,
#ifdef CONFIG_HOTPLUG_CPU

34
arch/arm/mach-socfpga/socfpga.c
View file

@ -27,43 +27,10 @@
#include "core.h"
void __iomem *socfpga_scu_base_addr = ((void __iomem *)(SOCFPGA_SCU_VIRT_BASE));
void __iomem *sys_manager_base_addr;
void __iomem *rst_manager_base_addr;
unsigned long socfpga_cpu1start_addr;
static struct map_desc scu_io_desc __initdata = {
.virtual = SOCFPGA_SCU_VIRT_BASE,
.pfn = 0, /* run-time */
.length = SZ_8K,
.type = MT_DEVICE,
};
static struct map_desc uart_io_desc __initdata = {
.virtual = 0xfec02000,
.pfn = __phys_to_pfn(0xffc02000),
.length = SZ_8K,
.type = MT_DEVICE,
};
static void __init socfpga_scu_map_io(void)
{
unsigned long base;
/* Get SCU base */
asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (base));
scu_io_desc.pfn = __phys_to_pfn(base);
iotable_init(&scu_io_desc, 1);
}
static void __init socfpga_map_io(void)
{
socfpga_scu_map_io();
iotable_init(&uart_io_desc, 1);
early_printk("Early printk initialized\n");
}
void __init socfpga_sysmgr_init(void)
{
struct device_node *np;
@ -112,7 +79,6 @@ DT_MACHINE_START(SOCFPGA, "Altera SOCFPGA")
.l2c_aux_val = 0,
.l2c_aux_mask = ~0,
.smp = smp_ops(socfpga_smp_ops),
.map_io = socfpga_map_io,
.init_irq = socfpga_init_irq,
.restart = socfpga_cyclone5_restart,
.dt_compat = altera_dt_match,