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MIPS: Lantiq: Deactivate most of the devices by default
When the SoC starts up most of the devices should be deactivated by the PMU, they should be activated when they get used by their drivers. Some devices should not get deactivate at startup like the serial, register them in a special way. Signed-off-by: Hauke Mehrtens <hauke.mehrtens@lantiq.com> Acked-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/11386/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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parent
61e371d822
commit
95135bfa7e
1 changed files with 28 additions and 21 deletions
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@ -286,8 +286,8 @@ static int clkout_enable(struct clk *clk)
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}
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/* manage the clock gates via PMU */
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static void clkdev_add_pmu(const char *dev, const char *con,
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unsigned int module, unsigned int bits)
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static void clkdev_add_pmu(const char *dev, const char *con, bool deactivate,
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unsigned int module, unsigned int bits)
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{
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struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL);
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@ -298,6 +298,13 @@ static void clkdev_add_pmu(const char *dev, const char *con,
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clk->disable = pmu_disable;
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clk->module = module;
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clk->bits = bits;
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if (deactivate) {
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/*
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* Disable it during the initialization. Module should enable
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* when used
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*/
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pmu_disable(clk);
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}
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clkdev_add(&clk->cl);
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}
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@ -416,13 +423,13 @@ void __init ltq_soc_init(void)
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ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_BUSCON0) & ~EBU_WRDIS, LTQ_EBU_BUSCON0);
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/* add our generic xway clocks */
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clkdev_add_pmu("10000000.fpi", NULL, 0, PMU_FPI);
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clkdev_add_pmu("1e100400.serial", NULL, 0, PMU_ASC0);
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clkdev_add_pmu("1e100a00.gptu", NULL, 0, PMU_GPT);
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clkdev_add_pmu("1e100bb0.stp", NULL, 0, PMU_STP);
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clkdev_add_pmu("1e104100.dma", NULL, 0, PMU_DMA);
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clkdev_add_pmu("1e100800.spi", NULL, 0, PMU_SPI);
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clkdev_add_pmu("1e105300.ebu", NULL, 0, PMU_EBU);
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clkdev_add_pmu("10000000.fpi", NULL, 0, 0, PMU_FPI);
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clkdev_add_pmu("1e100400.serial", NULL, 0, 0, PMU_ASC0);
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clkdev_add_pmu("1e100a00.gptu", NULL, 1, 0, PMU_GPT);
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clkdev_add_pmu("1e100bb0.stp", NULL, 1, 0, PMU_STP);
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clkdev_add_pmu("1e104100.dma", NULL, 1, 0, PMU_DMA);
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clkdev_add_pmu("1e100800.spi", NULL, 1, 0, PMU_SPI);
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clkdev_add_pmu("1e105300.ebu", NULL, 0, 0, PMU_EBU);
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clkdev_add_clkout();
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/* add the soc dependent clocks */
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@ -430,11 +437,11 @@ void __init ltq_soc_init(void)
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ifccr = CGU_IFCCR_VR9;
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pcicr = CGU_PCICR_VR9;
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} else {
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clkdev_add_pmu("1e180000.etop", NULL, 0, PMU_PPE);
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clkdev_add_pmu("1e180000.etop", NULL, 1, 0, PMU_PPE);
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}
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if (!of_machine_is_compatible("lantiq,ase")) {
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clkdev_add_pmu("1e100c00.serial", NULL, 0, PMU_ASC1);
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clkdev_add_pmu("1e100c00.serial", NULL, 0, 0, PMU_ASC1);
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clkdev_add_pci();
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}
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@ -446,25 +453,25 @@ void __init ltq_soc_init(void)
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clkdev_add_static(CLOCK_133M, CLOCK_133M,
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CLOCK_133M, CLOCK_133M);
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clkdev_add_cgu("1e180000.etop", "ephycgu", CGU_EPHY),
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clkdev_add_pmu("1e180000.etop", "ephy", 0, PMU_EPHY);
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clkdev_add_pmu("1e180000.etop", "ephy", 1, 0, PMU_EPHY);
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} else if (of_machine_is_compatible("lantiq,vr9")) {
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clkdev_add_static(ltq_vr9_cpu_hz(), ltq_vr9_fpi_hz(),
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ltq_vr9_fpi_hz(), ltq_vr9_pp32_hz());
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clkdev_add_pmu("1d900000.pcie", "phy", 1, PMU1_PCIE_PHY);
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clkdev_add_pmu("1d900000.pcie", "bus", 0, PMU_PCIE_CLK);
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clkdev_add_pmu("1d900000.pcie", "msi", 1, PMU1_PCIE_MSI);
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clkdev_add_pmu("1d900000.pcie", "pdi", 1, PMU1_PCIE_PDI);
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clkdev_add_pmu("1d900000.pcie", "ctl", 1, PMU1_PCIE_CTL);
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clkdev_add_pmu("1d900000.pcie", "ahb", 0, PMU_AHBM | PMU_AHBS);
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clkdev_add_pmu("1e108000.eth", NULL, 0,
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clkdev_add_pmu("1d900000.pcie", "phy", 1, 1, PMU1_PCIE_PHY);
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clkdev_add_pmu("1d900000.pcie", "bus", 1, 0, PMU_PCIE_CLK);
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clkdev_add_pmu("1d900000.pcie", "msi", 1, 1, PMU1_PCIE_MSI);
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clkdev_add_pmu("1d900000.pcie", "pdi", 1, 1, PMU1_PCIE_PDI);
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clkdev_add_pmu("1d900000.pcie", "ctl", 1, 1, PMU1_PCIE_CTL);
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clkdev_add_pmu("1d900000.pcie", "ahb", 1, 0, PMU_AHBM | PMU_AHBS);
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clkdev_add_pmu("1e108000.eth", NULL, 1, 0,
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PMU_SWITCH | PMU_PPE_DPLUS | PMU_PPE_DPLUM |
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PMU_PPE_EMA | PMU_PPE_TC | PMU_PPE_SLL01 |
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PMU_PPE_QSB | PMU_PPE_TOP);
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clkdev_add_pmu("1f203000.rcu", "gphy", 0, PMU_GPHY);
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clkdev_add_pmu("1f203000.rcu", "gphy", 1, 0, PMU_GPHY);
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} else if (of_machine_is_compatible("lantiq,ar9")) {
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clkdev_add_static(ltq_ar9_cpu_hz(), ltq_ar9_fpi_hz(),
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ltq_ar9_fpi_hz(), CLOCK_250M);
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clkdev_add_pmu("1e180000.etop", "switch", 0, PMU_SWITCH);
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clkdev_add_pmu("1e180000.etop", "switch", 1, 0, PMU_SWITCH);
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} else {
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clkdev_add_static(ltq_danube_cpu_hz(), ltq_danube_fpi_hz(),
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ltq_danube_fpi_hz(), ltq_danube_pp32_hz());
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