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spi: Add bindings for Lightning Mountain SoC

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Add support to SPI controller on Intel Atom based Lightning Mountain
SoC which reuses the Lantiq SPI controller IP.

Signed-off-by: Dilip Kota <eswara.kota@linux.intel.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/7d644e5d03ef534f719763e5c823c1673e53d1a5.1594957019.git.eswara.kota@linux.intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Dilip Kota 2020-07-17 14:27:56 +08:00 committed by Mark Brown
parent 040f7f9729
commit 956284a304
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GPG key ID: 24D68B725D5487D0
1 changed files with 19 additions and 2 deletions
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21
Documentation/devicetree/bindings/spi/spi-lantiq-ssc.txt
View file

@ -1,11 +1,17 @@
Lantiq Synchronous Serial Controller (SSC) SPI master driver
Required properties:
- compatible: "lantiq,ase-spi", "lantiq,falcon-spi", "lantiq,xrx100-spi"
- compatible: "lantiq,ase-spi", "lantiq,falcon-spi", "lantiq,xrx100-spi",
"intel,lgm-spi"
- #address-cells: see spi-bus.txt
- #size-cells: see spi-bus.txt
- reg: address and length of the spi master registers
- interrupts: should contain the "spi_rx", "spi_tx" and "spi_err" interrupt.
- interrupts:
For compatible "intel,lgm-ssc" - the common interrupt number for
all of tx rx & err interrupts.
or
For rest of the compatibles, should contain the "spi_rx", "spi_tx" and
"spi_err" interrupt.
Optional properties:
@ -27,3 +33,14 @@ spi: spi@e100800 {
num-cs = <6>;
base-cs = <1>;
};
ssc0: spi@e0800000 {
compatible = "intel,lgm-spi";
reg = <0xe0800000 0x400>;
interrupt-parent = <&ioapic1>;
interrupts = <35 1>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&cgu0 LGM_CLK_NGI>, <&cgu0 LGM_GCLK_SSC0>;
clock-names = "freq", "gate";
};