nios2: Device tree support
Add device tree support to arch/nios2. Signed-off-by: Ley Foon Tan <lftan@altera.com>
This commit is contained in:
Ley Foon Tan
parent
eea9507a69
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* Nios II Processor Binding
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This binding specifies what properties available in the device tree
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representation of a Nios II Processor Core.
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Users can use sopc2dts tool for generating device tree sources (dts) from a
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Qsys system. See more detail in: http://www.alterawiki.com/wiki/Sopc2dts
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Required properties:
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- compatible: Compatible property value should be "altr,nios2-1.0".
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- reg: Contains CPU index.
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- interrupt-controller: Specifies that the node is an interrupt controller
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- #interrupt-cells: Specifies the number of cells needed to encode an
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interrupt source, should be 1.
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- clock-frequency: Contains the clock frequency for CPU, in Hz.
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- dcache-line-size: Contains data cache line size.
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- icache-line-size: Contains instruction line size.
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- dcache-size: Contains data cache size.
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- icache-size: Contains instruction cache size.
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- altr,pid-num-bits: Specifies the number of bits to use to represent the process
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identifier (PID).
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- altr,tlb-num-ways: Specifies the number of set-associativity ways in the TLB.
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- altr,tlb-num-entries: Specifies the number of entries in the TLB.
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- altr,tlb-ptr-sz: Specifies size of TLB pointer.
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- altr,has-mul: Specifies CPU hardware multipy support, should be 1.
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- altr,has-mmu: Specifies CPU support MMU support, should be 1.
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- altr,has-initda: Specifies CPU support initda instruction, should be 1.
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- altr,reset-addr: Specifies CPU reset address
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- altr,fast-tlb-miss-addr: Specifies CPU fast TLB miss exception address
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- altr,exception-addr: Specifies CPU exception address
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Optional properties:
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- altr,has-div: Specifies CPU hardware divide support
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- altr,implementation: Nios II core implementation, this should be "fast";
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Example:
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cpu@0x0 {
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device_type = "cpu";
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compatible = "altr,nios2-1.0";
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reg = <0>;
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interrupt-controller;
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#interrupt-cells = <1>;
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clock-frequency = <125000000>;
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dcache-line-size = <32>;
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icache-line-size = <32>;
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dcache-size = <32768>;
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icache-size = <32768>;
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altr,implementation = "fast";
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altr,pid-num-bits = <8>;
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altr,tlb-num-ways = <16>;
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altr,tlb-num-entries = <128>;
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altr,tlb-ptr-sz = <7>;
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altr,has-div = <1>;
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altr,has-mul = <1>;
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altr,reset-addr = <0xc2800000>;
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altr,fast-tlb-miss-addr = <0xc7fff400>;
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altr,exception-addr = <0xd0000020>;
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altr,has-initda = <1>;
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altr,has-mmu = <1>;
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};
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Altera Timer
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Required properties:
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- compatible : should be "altr,timer-1.0"
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- reg : Specifies base physical address and size of the registers.
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- interrupt-parent: phandle of the interrupt controller
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- interrupts : Should contain the timer interrupt number
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- clock-frequency : The frequency of the clock that drives the counter, in Hz.
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Example:
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timer {
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compatible = "altr,timer-1.0";
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reg = <0x00400000 0x00000020>;
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interrupt-parent = <&cpu>;
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interrupts = <11>;
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clock-frequency = <125000000>;
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};
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/*
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* Copyright (C) 2013 Altera Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*
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* This file is generated by sopc2dts.
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*/
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/dts-v1/;
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/ {
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model = "altr,qsys_ghrd_3c120";
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compatible = "altr,qsys_ghrd_3c120";
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#address-cells = <1>;
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#size-cells = <1>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu: cpu@0x0 {
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device_type = "cpu";
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compatible = "altr,nios2-1.0";
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reg = <0x00000000>;
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interrupt-controller;
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#interrupt-cells = <1>;
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clock-frequency = <125000000>;
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dcache-line-size = <32>;
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icache-line-size = <32>;
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dcache-size = <32768>;
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icache-size = <32768>;
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altr,implementation = "fast";
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altr,pid-num-bits = <8>;
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altr,tlb-num-ways = <16>;
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altr,tlb-num-entries = <128>;
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altr,tlb-ptr-sz = <7>;
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altr,has-div = <1>;
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altr,has-mul = <1>;
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altr,reset-addr = <0xc2800000>;
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altr,fast-tlb-miss-addr = <0xc7fff400>;
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altr,exception-addr = <0xd0000020>;
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altr,has-initda = <1>;
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altr,has-mmu = <1>;
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};
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};
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memory@0 {
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device_type = "memory";
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reg = <0x10000000 0x08000000>,
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<0x07fff400 0x00000400>;
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};
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sopc@0 {
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device_type = "soc";
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ranges;
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "altr,avalon", "simple-bus";
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bus-frequency = <125000000>;
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pb_cpu_to_io: bridge@0x8000000 {
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compatible = "simple-bus";
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reg = <0x08000000 0x00800000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x00002000 0x08002000 0x00002000>,
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<0x00004000 0x08004000 0x00000400>,
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<0x00004400 0x08004400 0x00000040>,
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<0x00004800 0x08004800 0x00000040>,
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<0x00004c80 0x08004c80 0x00000020>,
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<0x00004d50 0x08004d50 0x00000008>,
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<0x00008000 0x08008000 0x00000020>,
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<0x00400000 0x08400000 0x00000020>;
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timer_1ms: timer@0x400000 {
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compatible = "altr,timer-1.0";
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reg = <0x00400000 0x00000020>;
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interrupt-parent = <&cpu>;
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interrupts = <11>;
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clock-frequency = <125000000>;
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};
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timer_0: timer@0x8000 {
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compatible = "altr,timer-1.0";
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reg = < 0x00008000 0x00000020 >;
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interrupt-parent = < &cpu >;
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interrupts = < 5 >;
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clock-frequency = < 125000000 >;
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};
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jtag_uart: serial@0x4d50 {
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compatible = "altr,juart-1.0";
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reg = <0x00004d50 0x00000008>;
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interrupt-parent = <&cpu>;
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interrupts = <1>;
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};
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tse_mac: ethernet@0x4000 {
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compatible = "altr,tse-1.0";
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reg = <0x00004000 0x00000400>,
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<0x00004400 0x00000040>,
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<0x00004800 0x00000040>,
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<0x00002000 0x00002000>;
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reg-names = "control_port", "rx_csr", "tx_csr", "s1";
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interrupt-parent = <&cpu>;
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interrupts = <2 3>;
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interrupt-names = "rx_irq", "tx_irq";
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rx-fifo-depth = <8192>;
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tx-fifo-depth = <8192>;
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max-frame-size = <1518>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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phy-mode = "rgmii-id";
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phy-handle = <&phy0>;
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tse_mac_mdio: mdio {
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compatible = "altr,tse-mdio";
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#address-cells = <1>;
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#size-cells = <0>;
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phy0: ethernet-phy@18 {
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reg = <18>;
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device_type = "ethernet-phy";
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};
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};
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};
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uart: serial@0x4c80 {
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compatible = "altr,uart-1.0";
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reg = <0x00004c80 0x00000020>;
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interrupt-parent = <&cpu>;
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interrupts = <10>;
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current-speed = <115200>;
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clock-frequency = <62500000>;
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};
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};
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cfi_flash_64m: flash@0x0 {
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compatible = "cfi-flash";
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reg = <0x00000000 0x04000000>;
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bank-width = <2>;
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device-width = <1>;
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#address-cells = <1>;
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#size-cells = <1>;
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partition@800000 {
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reg = <0x00800000 0x01e00000>;
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label = "JFFS2 Filesystem";
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};
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};
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};
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chosen {
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bootargs = "debug console=ttyJ0,115200";
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};
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};
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/*
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* Copyright (C) 2011 Thomas Chou <thomas@wytron.com.tw>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*
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*/
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.section .dtb.init.rodata,"a"
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.incbin "arch/nios2/boot/system.dtb"
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/*
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* Device tree support
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*
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* Copyright (C) 2013 Altera Corporation
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* Copyright (C) 2010 Thomas Chou <thomas@wytron.com.tw>
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*
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* Based on MIPS support for CONFIG_OF device tree support
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*
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* Copyright (C) 2010 Cisco Systems Inc. <dediao@cisco.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*
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*/
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#include <linux/init.h>
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#include <linux/types.h>
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#include <linux/bootmem.h>
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#include <linux/of.h>
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#include <linux/of_fdt.h>
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#include <linux/io.h>
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#include <asm/sections.h>
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void __init early_init_dt_add_memory_arch(u64 base, u64 size)
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{
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u64 kernel_start = (u64)virt_to_phys(_text);
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if (!memory_size &&
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(kernel_start >= base) && (kernel_start < (base + size)))
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memory_size = size;
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}
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void * __init early_init_dt_alloc_memory_arch(u64 size, u64 align)
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{
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return alloc_bootmem_align(size, align);
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}
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void __init early_init_devtree(void *params)
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{
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__be32 *dtb = (u32 *)__dtb_start;
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#if defined(CONFIG_NIOS2_DTB_AT_PHYS_ADDR)
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if (be32_to_cpup((__be32 *)CONFIG_NIOS2_DTB_PHYS_ADDR) ==
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OF_DT_HEADER) {
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params = (void *)CONFIG_NIOS2_DTB_PHYS_ADDR;
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early_init_dt_scan(params);
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return;
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}
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#endif
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if (be32_to_cpu((__be32) *dtb) == OF_DT_HEADER)
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params = (void *)__dtb_start;
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early_init_dt_scan(params);
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}
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/*
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* Copyright (C) 2013 Altera Corporation
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* Copyright (C) 2011 Thomas Chou
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* Copyright (C) 2011 Walter Goossens
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*
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* This file is subject to the terms and conditions of the GNU General
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* Public License. See the file COPYING in the main directory of this
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* archive for more details.
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*/
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#include <linux/init.h>
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#include <linux/of_platform.h>
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#include <linux/of_address.h>
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#include <linux/of_fdt.h>
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#include <linux/err.h>
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#include <linux/slab.h>
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#include <linux/sys_soc.h>
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#include <linux/io.h>
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static int __init nios2_soc_device_init(void)
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{
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struct soc_device *soc_dev;
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struct soc_device_attribute *soc_dev_attr;
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const char *machine;
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soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
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if (soc_dev_attr) {
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machine = of_flat_dt_get_machine_name();
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if (machine)
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soc_dev_attr->machine = kasprintf(GFP_KERNEL, "%s",
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machine);
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soc_dev_attr->family = "Nios II";
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soc_dev = soc_device_register(soc_dev_attr);
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if (IS_ERR(soc_dev)) {
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kfree(soc_dev_attr->machine);
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kfree(soc_dev_attr);
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}
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}
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return of_platform_populate(NULL, of_default_bus_match_table,
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NULL, NULL);
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}
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device_initcall(nios2_soc_device_init);
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