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iio: adc: stm32: add support for STM32H7
Add support for STM32H7 Analog to Digital Converter. It has up to 20 external channels, resolution ranges from 8 to 16bits. Either bus or asynchronous adc clock may be used. Add registers & bitfields definition. Also add new configuration options to enter/exit powerdown and perform self-calibration. Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
This commit is contained in:
Fabrice Gasnier
Jonathan Cameron
parent
204a6a25db
commit
95e339b6e8
3 changed files with 701 additions and 4 deletions
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@ -49,6 +49,23 @@
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/* STM32 F4 maximum analog clock rate (from datasheet) */
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#define STM32F4_ADC_MAX_CLK_RATE 36000000
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/* STM32H7 - common registers for all ADC instances */
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#define STM32H7_ADC_CSR (STM32_ADCX_COMN_OFFSET + 0x00)
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#define STM32H7_ADC_CCR (STM32_ADCX_COMN_OFFSET + 0x08)
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/* STM32H7_ADC_CSR - bit fields */
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#define STM32H7_EOC_SLV BIT(18)
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#define STM32H7_EOC_MST BIT(2)
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/* STM32H7_ADC_CCR - bit fields */
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#define STM32H7_PRESC_SHIFT 18
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#define STM32H7_PRESC_MASK GENMASK(21, 18)
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#define STM32H7_CKMODE_SHIFT 16
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#define STM32H7_CKMODE_MASK GENMASK(17, 16)
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/* STM32 H7 maximum analog clock rate (from datasheet) */
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#define STM32H7_ADC_MAX_CLK_RATE 72000000
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/**
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* stm32_adc_common_regs - stm32 common registers, compatible dependent data
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* @csr: common status register offset
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@ -80,6 +97,7 @@ struct stm32_adc_priv_cfg {
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* @irq: irq for ADC block
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* @domain: irq domain reference
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* @aclk: clock reference for the analog circuitry
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* @bclk: bus clock common for all ADCs, depends on part used
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* @vref: regulator reference
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* @cfg: compatible configuration data
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* @common: common data for all ADC instances
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@ -88,6 +106,7 @@ struct stm32_adc_priv {
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int irq;
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struct irq_domain *domain;
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struct clk *aclk;
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struct clk *bclk;
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struct regulator *vref;
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const struct stm32_adc_priv_cfg *cfg;
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struct stm32_adc_common common;
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@ -129,6 +148,7 @@ static int stm32f4_adc_clk_sel(struct platform_device *pdev,
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return -EINVAL;
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}
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priv->common.rate = rate;
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val = readl_relaxed(priv->common.base + STM32F4_ADC_CCR);
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val &= ~STM32F4_ADC_ADCPRE_MASK;
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val |= i << STM32F4_ADC_ADCPRE_SHIFT;
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@ -140,6 +160,111 @@ static int stm32f4_adc_clk_sel(struct platform_device *pdev,
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return 0;
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}
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/**
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* struct stm32h7_adc_ck_spec - specification for stm32h7 adc clock
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* @ckmode: ADC clock mode, Async or sync with prescaler.
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* @presc: prescaler bitfield for async clock mode
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* @div: prescaler division ratio
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*/
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struct stm32h7_adc_ck_spec {
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u32 ckmode;
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u32 presc;
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int div;
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};
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const struct stm32h7_adc_ck_spec stm32h7_adc_ckmodes_spec[] = {
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/* 00: CK_ADC[1..3]: Asynchronous clock modes */
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{ 0, 0, 1 },
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{ 0, 1, 2 },
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{ 0, 2, 4 },
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{ 0, 3, 6 },
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{ 0, 4, 8 },
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{ 0, 5, 10 },
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{ 0, 6, 12 },
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{ 0, 7, 16 },
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{ 0, 8, 32 },
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{ 0, 9, 64 },
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{ 0, 10, 128 },
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{ 0, 11, 256 },
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/* HCLK used: Synchronous clock modes (1, 2 or 4 prescaler) */
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{ 1, 0, 1 },
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{ 2, 0, 2 },
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{ 3, 0, 4 },
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};
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static int stm32h7_adc_clk_sel(struct platform_device *pdev,
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struct stm32_adc_priv *priv)
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{
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u32 ckmode, presc, val;
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unsigned long rate;
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int i, div;
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/* stm32h7 bus clock is common for all ADC instances (mandatory) */
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if (!priv->bclk) {
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dev_err(&pdev->dev, "No 'bus' clock found\n");
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return -ENOENT;
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}
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/*
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* stm32h7 can use either 'bus' or 'adc' clock for analog circuitry.
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* So, choice is to have bus clock mandatory and adc clock optional.
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* If optional 'adc' clock has been found, then try to use it first.
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*/
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if (priv->aclk) {
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/*
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* Asynchronous clock modes (e.g. ckmode == 0)
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* From spec: PLL output musn't exceed max rate
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*/
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rate = clk_get_rate(priv->aclk);
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for (i = 0; i < ARRAY_SIZE(stm32h7_adc_ckmodes_spec); i++) {
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ckmode = stm32h7_adc_ckmodes_spec[i].ckmode;
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presc = stm32h7_adc_ckmodes_spec[i].presc;
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div = stm32h7_adc_ckmodes_spec[i].div;
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if (ckmode)
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continue;
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if ((rate / div) <= STM32H7_ADC_MAX_CLK_RATE)
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goto out;
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}
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}
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/* Synchronous clock modes (e.g. ckmode is 1, 2 or 3) */
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rate = clk_get_rate(priv->bclk);
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for (i = 0; i < ARRAY_SIZE(stm32h7_adc_ckmodes_spec); i++) {
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ckmode = stm32h7_adc_ckmodes_spec[i].ckmode;
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presc = stm32h7_adc_ckmodes_spec[i].presc;
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div = stm32h7_adc_ckmodes_spec[i].div;
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if (!ckmode)
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continue;
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if ((rate / div) <= STM32H7_ADC_MAX_CLK_RATE)
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goto out;
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}
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dev_err(&pdev->dev, "adc clk selection failed\n");
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return -EINVAL;
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out:
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/* rate used later by each ADC instance to control BOOST mode */
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priv->common.rate = rate;
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/* Set common clock mode and prescaler */
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val = readl_relaxed(priv->common.base + STM32H7_ADC_CCR);
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val &= ~(STM32H7_CKMODE_MASK | STM32H7_PRESC_MASK);
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val |= ckmode << STM32H7_CKMODE_SHIFT;
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val |= presc << STM32H7_PRESC_SHIFT;
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writel_relaxed(val, priv->common.base + STM32H7_ADC_CCR);
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dev_dbg(&pdev->dev, "Using %s clock/%d source at %ld kHz\n",
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ckmode ? "bus" : "adc", div, rate / (div * 1000));
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return 0;
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}
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/* STM32F4 common registers definitions */
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static const struct stm32_adc_common_regs stm32f4_adc_common_regs = {
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.csr = STM32F4_ADC_CSR,
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@ -148,6 +273,13 @@ static const struct stm32_adc_common_regs stm32f4_adc_common_regs = {
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.eoc3_msk = STM32F4_EOC3,
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};
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/* STM32H7 common registers definitions */
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static const struct stm32_adc_common_regs stm32h7_adc_common_regs = {
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.csr = STM32H7_ADC_CSR,
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.eoc1_msk = STM32H7_EOC_MST,
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.eoc2_msk = STM32H7_EOC_SLV,
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};
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/* ADC common interrupt for all instances */
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static void stm32_adc_irq_handler(struct irq_desc *desc)
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{
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@ -291,13 +423,32 @@ static int stm32_adc_probe(struct platform_device *pdev)
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}
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}
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priv->bclk = devm_clk_get(&pdev->dev, "bus");
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if (IS_ERR(priv->bclk)) {
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ret = PTR_ERR(priv->bclk);
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if (ret == -ENOENT) {
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priv->bclk = NULL;
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} else {
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dev_err(&pdev->dev, "Can't get 'bus' clock\n");
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goto err_aclk_disable;
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}
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}
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if (priv->bclk) {
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ret = clk_prepare_enable(priv->bclk);
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if (ret < 0) {
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dev_err(&pdev->dev, "adc clk enable failed\n");
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goto err_aclk_disable;
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}
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}
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ret = priv->cfg->clk_sel(pdev, priv);
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if (ret < 0)
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goto err_clk_disable;
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goto err_bclk_disable;
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ret = stm32_adc_irq_probe(pdev, priv);
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if (ret < 0)
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goto err_clk_disable;
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goto err_bclk_disable;
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platform_set_drvdata(pdev, &priv->common);
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@ -312,7 +463,11 @@ static int stm32_adc_probe(struct platform_device *pdev)
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err_irq_remove:
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stm32_adc_irq_remove(pdev, priv);
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err_clk_disable:
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err_bclk_disable:
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if (priv->bclk)
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clk_disable_unprepare(priv->bclk);
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err_aclk_disable:
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if (priv->aclk)
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clk_disable_unprepare(priv->aclk);
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@ -329,6 +484,8 @@ static int stm32_adc_remove(struct platform_device *pdev)
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of_platform_depopulate(&pdev->dev);
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stm32_adc_irq_remove(pdev, priv);
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if (priv->bclk)
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clk_disable_unprepare(priv->bclk);
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if (priv->aclk)
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clk_disable_unprepare(priv->aclk);
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regulator_disable(priv->vref);
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@ -341,10 +498,18 @@ static const struct stm32_adc_priv_cfg stm32f4_adc_priv_cfg = {
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.clk_sel = stm32f4_adc_clk_sel,
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};
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static const struct stm32_adc_priv_cfg stm32h7_adc_priv_cfg = {
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.regs = &stm32h7_adc_common_regs,
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.clk_sel = stm32h7_adc_clk_sel,
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};
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static const struct of_device_id stm32_adc_of_match[] = {
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{
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.compatible = "st,stm32f4-adc-core",
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.data = (void *)&stm32f4_adc_priv_cfg
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}, {
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.compatible = "st,stm32h7-adc-core",
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.data = (void *)&stm32h7_adc_priv_cfg
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}, {
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},
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};
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@ -43,11 +43,13 @@
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* struct stm32_adc_common - stm32 ADC driver common data (for all instances)
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* @base: control registers base cpu addr
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* @phys_base: control registers base physical addr
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* @rate: clock rate used for analog circuitry
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* @vref_mv: vref voltage (mv)
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*/
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struct stm32_adc_common {
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void __iomem *base;
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phys_addr_t phys_base;
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unsigned long rate;
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int vref_mv;
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};
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@ -31,6 +31,7 @@
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#include <linux/iio/triggered_buffer.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/iopoll.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/of.h>
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@ -77,6 +78,78 @@
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#define STM32F4_DMA BIT(8)
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#define STM32F4_ADON BIT(0)
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/* STM32H7 - Registers for each ADC instance */
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#define STM32H7_ADC_ISR 0x00
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#define STM32H7_ADC_IER 0x04
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#define STM32H7_ADC_CR 0x08
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#define STM32H7_ADC_CFGR 0x0C
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#define STM32H7_ADC_PCSEL 0x1C
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#define STM32H7_ADC_SQR1 0x30
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#define STM32H7_ADC_SQR2 0x34
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#define STM32H7_ADC_SQR3 0x38
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#define STM32H7_ADC_SQR4 0x3C
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#define STM32H7_ADC_DR 0x40
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#define STM32H7_ADC_CALFACT 0xC4
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#define STM32H7_ADC_CALFACT2 0xC8
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/* STM32H7_ADC_ISR - bit fields */
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#define STM32H7_EOC BIT(2)
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#define STM32H7_ADRDY BIT(0)
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/* STM32H7_ADC_IER - bit fields */
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#define STM32H7_EOCIE STM32H7_EOC
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/* STM32H7_ADC_CR - bit fields */
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#define STM32H7_ADCAL BIT(31)
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#define STM32H7_ADCALDIF BIT(30)
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#define STM32H7_DEEPPWD BIT(29)
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#define STM32H7_ADVREGEN BIT(28)
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#define STM32H7_LINCALRDYW6 BIT(27)
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#define STM32H7_LINCALRDYW5 BIT(26)
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#define STM32H7_LINCALRDYW4 BIT(25)
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#define STM32H7_LINCALRDYW3 BIT(24)
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#define STM32H7_LINCALRDYW2 BIT(23)
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#define STM32H7_LINCALRDYW1 BIT(22)
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#define STM32H7_ADCALLIN BIT(16)
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#define STM32H7_BOOST BIT(8)
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#define STM32H7_ADSTP BIT(4)
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#define STM32H7_ADSTART BIT(2)
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#define STM32H7_ADDIS BIT(1)
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#define STM32H7_ADEN BIT(0)
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/* STM32H7_ADC_CFGR bit fields */
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#define STM32H7_EXTEN_SHIFT 10
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#define STM32H7_EXTEN_MASK GENMASK(11, 10)
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#define STM32H7_EXTSEL_SHIFT 5
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#define STM32H7_EXTSEL_MASK GENMASK(9, 5)
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#define STM32H7_RES_SHIFT 2
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#define STM32H7_RES_MASK GENMASK(4, 2)
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#define STM32H7_DMNGT_SHIFT 0
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#define STM32H7_DMNGT_MASK GENMASK(1, 0)
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enum stm32h7_adc_dmngt {
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STM32H7_DMNGT_DR_ONLY, /* Regular data in DR only */
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STM32H7_DMNGT_DMA_ONESHOT, /* DMA one shot mode */
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STM32H7_DMNGT_DFSDM, /* DFSDM mode */
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STM32H7_DMNGT_DMA_CIRC, /* DMA circular mode */
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};
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/* STM32H7_ADC_CALFACT - bit fields */
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#define STM32H7_CALFACT_D_SHIFT 16
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#define STM32H7_CALFACT_D_MASK GENMASK(26, 16)
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#define STM32H7_CALFACT_S_SHIFT 0
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#define STM32H7_CALFACT_S_MASK GENMASK(10, 0)
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/* STM32H7_ADC_CALFACT2 - bit fields */
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#define STM32H7_LINCALFACT_SHIFT 0
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#define STM32H7_LINCALFACT_MASK GENMASK(29, 0)
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/* Number of linear calibration shadow registers / LINCALRDYW control bits */
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#define STM32H7_LINCALFACT_NUM 6
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/* BOOST bit must be set on STM32H7 when ADC clock is above 20MHz */
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#define STM32H7_BOOST_CLKRATE 20000000UL
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#define STM32_ADC_MAX_SQ 16 /* SQ1..SQ16 */
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#define STM32_ADC_TIMEOUT_US 100000
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#define STM32_ADC_TIMEOUT (msecs_to_jiffies(STM32_ADC_TIMEOUT_US / 1000))
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@ -121,6 +194,18 @@ struct stm32_adc_trig_info {
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enum stm32_adc_extsel extsel;
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};
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/**
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* struct stm32_adc_calib - optional adc calibration data
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* @calfact_s: Calibration offset for single ended channels
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* @calfact_d: Calibration offset in differential
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* @lincalfact: Linearity calibration factor
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*/
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struct stm32_adc_calib {
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u32 calfact_s;
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u32 calfact_d;
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u32 lincalfact[STM32H7_LINCALFACT_NUM];
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};
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/**
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* stm32_adc_regs - stm32 ADC misc registers & bitfield desc
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* @reg: register offset
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@ -161,16 +246,22 @@ struct stm32_adc;
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* @adc_info: per instance input channels definitions
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* @trigs: external trigger sources
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* @clk_required: clock is required
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* @selfcalib: optional routine for self-calibration
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* @prepare: optional prepare routine (power-up, enable)
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* @start_conv: routine to start conversions
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* @stop_conv: routine to stop conversions
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* @unprepare: optional unprepare routine (disable, power-down)
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*/
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struct stm32_adc_cfg {
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const struct stm32_adc_regspec *regs;
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const struct stm32_adc_info *adc_info;
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struct stm32_adc_trig_info *trigs;
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bool clk_required;
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int (*selfcalib)(struct stm32_adc *);
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int (*prepare)(struct stm32_adc *);
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void (*start_conv)(struct stm32_adc *, bool dma);
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void (*stop_conv)(struct stm32_adc *);
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void (*unprepare)(struct stm32_adc *);
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};
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/**
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@ -191,6 +282,8 @@ struct stm32_adc_cfg {
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* @rx_buf: dma rx buffer cpu address
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* @rx_dma_buf: dma rx buffer bus address
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* @rx_buf_sz: dma rx buffer size
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* @pcsel bitmask to preselect channels on some devices
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* @cal: optional calibration data on some devices
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*/
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struct stm32_adc {
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struct stm32_adc_common *common;
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@ -209,6 +302,8 @@ struct stm32_adc {
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u8 *rx_buf;
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dma_addr_t rx_dma_buf;
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unsigned int rx_buf_sz;
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u32 pcsel;
|
||||
struct stm32_adc_calib cal;
|
||||
};
|
||||
|
||||
/**
|
||||
|
|
@ -240,6 +335,7 @@ struct stm32_adc_info {
|
|||
/*
|
||||
* Input definitions common for all instances:
|
||||
* stm32f4 can have up to 16 channels
|
||||
* stm32h7 can have up to 20 channels
|
||||
*/
|
||||
static const struct stm32_adc_chan_spec stm32_adc_channels[] = {
|
||||
{ IIO_VOLTAGE, 0, "in0" },
|
||||
|
|
@ -258,6 +354,10 @@ static const struct stm32_adc_chan_spec stm32_adc_channels[] = {
|
|||
{ IIO_VOLTAGE, 13, "in13" },
|
||||
{ IIO_VOLTAGE, 14, "in14" },
|
||||
{ IIO_VOLTAGE, 15, "in15" },
|
||||
{ IIO_VOLTAGE, 16, "in16" },
|
||||
{ IIO_VOLTAGE, 17, "in17" },
|
||||
{ IIO_VOLTAGE, 18, "in18" },
|
||||
{ IIO_VOLTAGE, 19, "in19" },
|
||||
};
|
||||
|
||||
static const unsigned int stm32f4_adc_resolutions[] = {
|
||||
|
|
@ -272,6 +372,18 @@ static const struct stm32_adc_info stm32f4_adc_info = {
|
|||
.num_res = ARRAY_SIZE(stm32f4_adc_resolutions),
|
||||
};
|
||||
|
||||
static const unsigned int stm32h7_adc_resolutions[] = {
|
||||
/* sorted values so the index matches RES[2:0] in STM32H7_ADC_CFGR */
|
||||
16, 14, 12, 10, 8,
|
||||
};
|
||||
|
||||
static const struct stm32_adc_info stm32h7_adc_info = {
|
||||
.channels = stm32_adc_channels,
|
||||
.max_channels = 20,
|
||||
.resolutions = stm32h7_adc_resolutions,
|
||||
.num_res = ARRAY_SIZE(stm32h7_adc_resolutions),
|
||||
};
|
||||
|
||||
/**
|
||||
* stm32f4_sq - describe regular sequence registers
|
||||
* - L: sequence len (register & bit field)
|
||||
|
|
@ -330,6 +442,58 @@ static const struct stm32_adc_regspec stm32f4_adc_regspec = {
|
|||
.res = { STM32F4_ADC_CR1, STM32F4_RES_MASK, STM32F4_RES_SHIFT },
|
||||
};
|
||||
|
||||
static const struct stm32_adc_regs stm32h7_sq[STM32_ADC_MAX_SQ + 1] = {
|
||||
/* L: len bit field description to be kept as first element */
|
||||
{ STM32H7_ADC_SQR1, GENMASK(3, 0), 0 },
|
||||
/* SQ1..SQ16 registers & bit fields (reg, mask, shift) */
|
||||
{ STM32H7_ADC_SQR1, GENMASK(10, 6), 6 },
|
||||
{ STM32H7_ADC_SQR1, GENMASK(16, 12), 12 },
|
||||
{ STM32H7_ADC_SQR1, GENMASK(22, 18), 18 },
|
||||
{ STM32H7_ADC_SQR1, GENMASK(28, 24), 24 },
|
||||
{ STM32H7_ADC_SQR2, GENMASK(4, 0), 0 },
|
||||
{ STM32H7_ADC_SQR2, GENMASK(10, 6), 6 },
|
||||
{ STM32H7_ADC_SQR2, GENMASK(16, 12), 12 },
|
||||
{ STM32H7_ADC_SQR2, GENMASK(22, 18), 18 },
|
||||
{ STM32H7_ADC_SQR2, GENMASK(28, 24), 24 },
|
||||
{ STM32H7_ADC_SQR3, GENMASK(4, 0), 0 },
|
||||
{ STM32H7_ADC_SQR3, GENMASK(10, 6), 6 },
|
||||
{ STM32H7_ADC_SQR3, GENMASK(16, 12), 12 },
|
||||
{ STM32H7_ADC_SQR3, GENMASK(22, 18), 18 },
|
||||
{ STM32H7_ADC_SQR3, GENMASK(28, 24), 24 },
|
||||
{ STM32H7_ADC_SQR4, GENMASK(4, 0), 0 },
|
||||
{ STM32H7_ADC_SQR4, GENMASK(10, 6), 6 },
|
||||
};
|
||||
|
||||
/* STM32H7 external trigger sources for all instances */
|
||||
static struct stm32_adc_trig_info stm32h7_adc_trigs[] = {
|
||||
{ TIM1_CH1, STM32_EXT0 },
|
||||
{ TIM1_CH2, STM32_EXT1 },
|
||||
{ TIM1_CH3, STM32_EXT2 },
|
||||
{ TIM2_CH2, STM32_EXT3 },
|
||||
{ TIM3_TRGO, STM32_EXT4 },
|
||||
{ TIM4_CH4, STM32_EXT5 },
|
||||
{ TIM8_TRGO, STM32_EXT7 },
|
||||
{ TIM8_TRGO2, STM32_EXT8 },
|
||||
{ TIM1_TRGO, STM32_EXT9 },
|
||||
{ TIM1_TRGO2, STM32_EXT10 },
|
||||
{ TIM2_TRGO, STM32_EXT11 },
|
||||
{ TIM4_TRGO, STM32_EXT12 },
|
||||
{ TIM6_TRGO, STM32_EXT13 },
|
||||
{ TIM3_CH4, STM32_EXT15 },
|
||||
{},
|
||||
};
|
||||
|
||||
static const struct stm32_adc_regspec stm32h7_adc_regspec = {
|
||||
.dr = STM32H7_ADC_DR,
|
||||
.ier_eoc = { STM32H7_ADC_IER, STM32H7_EOCIE },
|
||||
.isr_eoc = { STM32H7_ADC_ISR, STM32H7_EOC },
|
||||
.sqr = stm32h7_sq,
|
||||
.exten = { STM32H7_ADC_CFGR, STM32H7_EXTEN_MASK, STM32H7_EXTEN_SHIFT },
|
||||
.extsel = { STM32H7_ADC_CFGR, STM32H7_EXTSEL_MASK,
|
||||
STM32H7_EXTSEL_SHIFT },
|
||||
.res = { STM32H7_ADC_CFGR, STM32H7_RES_MASK, STM32H7_RES_SHIFT },
|
||||
};
|
||||
|
||||
/**
|
||||
* STM32 ADC registers access routines
|
||||
* @adc: stm32 adc instance
|
||||
|
|
@ -343,6 +507,12 @@ static u32 stm32_adc_readl(struct stm32_adc *adc, u32 reg)
|
|||
return readl_relaxed(adc->common->base + adc->offset + reg);
|
||||
}
|
||||
|
||||
#define stm32_adc_readl_addr(addr) stm32_adc_readl(adc, addr)
|
||||
|
||||
#define stm32_adc_readl_poll_timeout(reg, val, cond, sleep_us, timeout_us) \
|
||||
readx_poll_timeout(stm32_adc_readl_addr, reg, val, \
|
||||
cond, sleep_us, timeout_us)
|
||||
|
||||
static u16 stm32_adc_readw(struct stm32_adc *adc, u32 reg)
|
||||
{
|
||||
return readw_relaxed(adc->common->base + adc->offset + reg);
|
||||
|
|
@ -439,6 +609,324 @@ static void stm32f4_adc_stop_conv(struct stm32_adc *adc)
|
|||
STM32F4_ADON | STM32F4_DMA | STM32F4_DDS);
|
||||
}
|
||||
|
||||
static void stm32h7_adc_start_conv(struct stm32_adc *adc, bool dma)
|
||||
{
|
||||
enum stm32h7_adc_dmngt dmngt;
|
||||
unsigned long flags;
|
||||
u32 val;
|
||||
|
||||
if (dma)
|
||||
dmngt = STM32H7_DMNGT_DMA_CIRC;
|
||||
else
|
||||
dmngt = STM32H7_DMNGT_DR_ONLY;
|
||||
|
||||
spin_lock_irqsave(&adc->lock, flags);
|
||||
val = stm32_adc_readl(adc, STM32H7_ADC_CFGR);
|
||||
val = (val & ~STM32H7_DMNGT_MASK) | (dmngt << STM32H7_DMNGT_SHIFT);
|
||||
stm32_adc_writel(adc, STM32H7_ADC_CFGR, val);
|
||||
spin_unlock_irqrestore(&adc->lock, flags);
|
||||
|
||||
stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADSTART);
|
||||
}
|
||||
|
||||
static void stm32h7_adc_stop_conv(struct stm32_adc *adc)
|
||||
{
|
||||
struct iio_dev *indio_dev = iio_priv_to_dev(adc);
|
||||
int ret;
|
||||
u32 val;
|
||||
|
||||
stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADSTP);
|
||||
|
||||
ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_CR, val,
|
||||
!(val & (STM32H7_ADSTART)),
|
||||
100, STM32_ADC_TIMEOUT_US);
|
||||
if (ret)
|
||||
dev_warn(&indio_dev->dev, "stop failed\n");
|
||||
|
||||
stm32_adc_clr_bits(adc, STM32H7_ADC_CFGR, STM32H7_DMNGT_MASK);
|
||||
}
|
||||
|
||||
static void stm32h7_adc_exit_pwr_down(struct stm32_adc *adc)
|
||||
{
|
||||
/* Exit deep power down, then enable ADC voltage regulator */
|
||||
stm32_adc_clr_bits(adc, STM32H7_ADC_CR, STM32H7_DEEPPWD);
|
||||
stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADVREGEN);
|
||||
|
||||
if (adc->common->rate > STM32H7_BOOST_CLKRATE)
|
||||
stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_BOOST);
|
||||
|
||||
/* Wait for startup time */
|
||||
usleep_range(10, 20);
|
||||
}
|
||||
|
||||
static void stm32h7_adc_enter_pwr_down(struct stm32_adc *adc)
|
||||
{
|
||||
stm32_adc_clr_bits(adc, STM32H7_ADC_CR, STM32H7_BOOST);
|
||||
|
||||
/* Setting DEEPPWD disables ADC vreg and clears ADVREGEN */
|
||||
stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_DEEPPWD);
|
||||
}
|
||||
|
||||
static int stm32h7_adc_enable(struct stm32_adc *adc)
|
||||
{
|
||||
struct iio_dev *indio_dev = iio_priv_to_dev(adc);
|
||||
int ret;
|
||||
u32 val;
|
||||
|
||||
/* Clear ADRDY by writing one, then enable ADC */
|
||||
stm32_adc_set_bits(adc, STM32H7_ADC_ISR, STM32H7_ADRDY);
|
||||
stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADEN);
|
||||
|
||||
/* Poll for ADRDY to be set (after adc startup time) */
|
||||
ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_ISR, val,
|
||||
val & STM32H7_ADRDY,
|
||||
100, STM32_ADC_TIMEOUT_US);
|
||||
if (ret) {
|
||||
stm32_adc_clr_bits(adc, STM32H7_ADC_CR, STM32H7_ADEN);
|
||||
dev_err(&indio_dev->dev, "Failed to enable ADC\n");
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void stm32h7_adc_disable(struct stm32_adc *adc)
|
||||
{
|
||||
struct iio_dev *indio_dev = iio_priv_to_dev(adc);
|
||||
int ret;
|
||||
u32 val;
|
||||
|
||||
/* Disable ADC and wait until it's effectively disabled */
|
||||
stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADDIS);
|
||||
ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_CR, val,
|
||||
!(val & STM32H7_ADEN), 100,
|
||||
STM32_ADC_TIMEOUT_US);
|
||||
if (ret)
|
||||
dev_warn(&indio_dev->dev, "Failed to disable\n");
|
||||
}
|
||||
|
||||
/**
|
||||
* stm32h7_adc_read_selfcalib() - read calibration shadow regs, save result
|
||||
* @adc: stm32 adc instance
|
||||
*/
|
||||
static int stm32h7_adc_read_selfcalib(struct stm32_adc *adc)
|
||||
{
|
||||
struct iio_dev *indio_dev = iio_priv_to_dev(adc);
|
||||
int i, ret;
|
||||
u32 lincalrdyw_mask, val;
|
||||
|
||||
/* Enable adc so LINCALRDYW1..6 bits are writable */
|
||||
ret = stm32h7_adc_enable(adc);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/* Read linearity calibration */
|
||||
lincalrdyw_mask = STM32H7_LINCALRDYW6;
|
||||
for (i = STM32H7_LINCALFACT_NUM - 1; i >= 0; i--) {
|
||||
/* Clear STM32H7_LINCALRDYW[6..1]: transfer calib to CALFACT2 */
|
||||
stm32_adc_clr_bits(adc, STM32H7_ADC_CR, lincalrdyw_mask);
|
||||
|
||||
/* Poll: wait calib data to be ready in CALFACT2 register */
|
||||
ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_CR, val,
|
||||
!(val & lincalrdyw_mask),
|
||||
100, STM32_ADC_TIMEOUT_US);
|
||||
if (ret) {
|
||||
dev_err(&indio_dev->dev, "Failed to read calfact\n");
|
||||
goto disable;
|
||||
}
|
||||
|
||||
val = stm32_adc_readl(adc, STM32H7_ADC_CALFACT2);
|
||||
adc->cal.lincalfact[i] = (val & STM32H7_LINCALFACT_MASK);
|
||||
adc->cal.lincalfact[i] >>= STM32H7_LINCALFACT_SHIFT;
|
||||
|
||||
lincalrdyw_mask >>= 1;
|
||||
}
|
||||
|
||||
/* Read offset calibration */
|
||||
val = stm32_adc_readl(adc, STM32H7_ADC_CALFACT);
|
||||
adc->cal.calfact_s = (val & STM32H7_CALFACT_S_MASK);
|
||||
adc->cal.calfact_s >>= STM32H7_CALFACT_S_SHIFT;
|
||||
adc->cal.calfact_d = (val & STM32H7_CALFACT_D_MASK);
|
||||
adc->cal.calfact_d >>= STM32H7_CALFACT_D_SHIFT;
|
||||
|
||||
disable:
|
||||
stm32h7_adc_disable(adc);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* stm32h7_adc_restore_selfcalib() - Restore saved self-calibration result
|
||||
* @adc: stm32 adc instance
|
||||
* Note: ADC must be enabled, with no on-going conversions.
|
||||
*/
|
||||
static int stm32h7_adc_restore_selfcalib(struct stm32_adc *adc)
|
||||
{
|
||||
struct iio_dev *indio_dev = iio_priv_to_dev(adc);
|
||||
int i, ret;
|
||||
u32 lincalrdyw_mask, val;
|
||||
|
||||
val = (adc->cal.calfact_s << STM32H7_CALFACT_S_SHIFT) |
|
||||
(adc->cal.calfact_d << STM32H7_CALFACT_D_SHIFT);
|
||||
stm32_adc_writel(adc, STM32H7_ADC_CALFACT, val);
|
||||
|
||||
lincalrdyw_mask = STM32H7_LINCALRDYW6;
|
||||
for (i = STM32H7_LINCALFACT_NUM - 1; i >= 0; i--) {
|
||||
/*
|
||||
* Write saved calibration data to shadow registers:
|
||||
* Write CALFACT2, and set LINCALRDYW[6..1] bit to trigger
|
||||
* data write. Then poll to wait for complete transfer.
|
||||
*/
|
||||
val = adc->cal.lincalfact[i] << STM32H7_LINCALFACT_SHIFT;
|
||||
stm32_adc_writel(adc, STM32H7_ADC_CALFACT2, val);
|
||||
stm32_adc_set_bits(adc, STM32H7_ADC_CR, lincalrdyw_mask);
|
||||
ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_CR, val,
|
||||
val & lincalrdyw_mask,
|
||||
100, STM32_ADC_TIMEOUT_US);
|
||||
if (ret) {
|
||||
dev_err(&indio_dev->dev, "Failed to write calfact\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
/*
|
||||
* Read back calibration data, has two effects:
|
||||
* - It ensures bits LINCALRDYW[6..1] are kept cleared
|
||||
* for next time calibration needs to be restored.
|
||||
* - BTW, bit clear triggers a read, then check data has been
|
||||
* correctly written.
|
||||
*/
|
||||
stm32_adc_clr_bits(adc, STM32H7_ADC_CR, lincalrdyw_mask);
|
||||
ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_CR, val,
|
||||
!(val & lincalrdyw_mask),
|
||||
100, STM32_ADC_TIMEOUT_US);
|
||||
if (ret) {
|
||||
dev_err(&indio_dev->dev, "Failed to read calfact\n");
|
||||
return ret;
|
||||
}
|
||||
val = stm32_adc_readl(adc, STM32H7_ADC_CALFACT2);
|
||||
if (val != adc->cal.lincalfact[i] << STM32H7_LINCALFACT_SHIFT) {
|
||||
dev_err(&indio_dev->dev, "calfact not consistent\n");
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
lincalrdyw_mask >>= 1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* Fixed timeout value for ADC calibration.
|
||||
* worst cases:
|
||||
* - low clock frequency
|
||||
* - maximum prescalers
|
||||
* Calibration requires:
|
||||
* - 131,072 ADC clock cycle for the linear calibration
|
||||
* - 20 ADC clock cycle for the offset calibration
|
||||
*
|
||||
* Set to 100ms for now
|
||||
*/
|
||||
#define STM32H7_ADC_CALIB_TIMEOUT_US 100000
|
||||
|
||||
/**
|
||||
* stm32h7_adc_selfcalib() - Procedure to calibrate ADC (from power down)
|
||||
* @adc: stm32 adc instance
|
||||
* Exit from power down, calibrate ADC, then return to power down.
|
||||
*/
|
||||
static int stm32h7_adc_selfcalib(struct stm32_adc *adc)
|
||||
{
|
||||
struct iio_dev *indio_dev = iio_priv_to_dev(adc);
|
||||
int ret;
|
||||
u32 val;
|
||||
|
||||
stm32h7_adc_exit_pwr_down(adc);
|
||||
|
||||
/*
|
||||
* Select calibration mode:
|
||||
* - Offset calibration for single ended inputs
|
||||
* - No linearity calibration (do it later, before reading it)
|
||||
*/
|
||||
stm32_adc_clr_bits(adc, STM32H7_ADC_CR, STM32H7_ADCALDIF);
|
||||
stm32_adc_clr_bits(adc, STM32H7_ADC_CR, STM32H7_ADCALLIN);
|
||||
|
||||
/* Start calibration, then wait for completion */
|
||||
stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADCAL);
|
||||
ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_CR, val,
|
||||
!(val & STM32H7_ADCAL), 100,
|
||||
STM32H7_ADC_CALIB_TIMEOUT_US);
|
||||
if (ret) {
|
||||
dev_err(&indio_dev->dev, "calibration failed\n");
|
||||
goto pwr_dwn;
|
||||
}
|
||||
|
||||
/*
|
||||
* Select calibration mode, then start calibration:
|
||||
* - Offset calibration for differential input
|
||||
* - Linearity calibration (needs to be done only once for single/diff)
|
||||
* will run simultaneously with offset calibration.
|
||||
*/
|
||||
stm32_adc_set_bits(adc, STM32H7_ADC_CR,
|
||||
STM32H7_ADCALDIF | STM32H7_ADCALLIN);
|
||||
stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADCAL);
|
||||
ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_CR, val,
|
||||
!(val & STM32H7_ADCAL), 100,
|
||||
STM32H7_ADC_CALIB_TIMEOUT_US);
|
||||
if (ret) {
|
||||
dev_err(&indio_dev->dev, "calibration failed\n");
|
||||
goto pwr_dwn;
|
||||
}
|
||||
|
||||
stm32_adc_clr_bits(adc, STM32H7_ADC_CR,
|
||||
STM32H7_ADCALDIF | STM32H7_ADCALLIN);
|
||||
|
||||
/* Read calibration result for future reference */
|
||||
ret = stm32h7_adc_read_selfcalib(adc);
|
||||
|
||||
pwr_dwn:
|
||||
stm32h7_adc_enter_pwr_down(adc);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* stm32h7_adc_prepare() - Leave power down mode to enable ADC.
|
||||
* @adc: stm32 adc instance
|
||||
* Leave power down mode.
|
||||
* Enable ADC.
|
||||
* Restore calibration data.
|
||||
* Pre-select channels that may be used in PCSEL (required by input MUX / IO).
|
||||
*/
|
||||
static int stm32h7_adc_prepare(struct stm32_adc *adc)
|
||||
{
|
||||
int ret;
|
||||
|
||||
stm32h7_adc_exit_pwr_down(adc);
|
||||
|
||||
ret = stm32h7_adc_enable(adc);
|
||||
if (ret)
|
||||
goto pwr_dwn;
|
||||
|
||||
ret = stm32h7_adc_restore_selfcalib(adc);
|
||||
if (ret)
|
||||
goto disable;
|
||||
|
||||
stm32_adc_writel(adc, STM32H7_ADC_PCSEL, adc->pcsel);
|
||||
|
||||
return 0;
|
||||
|
||||
disable:
|
||||
stm32h7_adc_disable(adc);
|
||||
pwr_dwn:
|
||||
stm32h7_adc_enter_pwr_down(adc);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void stm32h7_adc_unprepare(struct stm32_adc *adc)
|
||||
{
|
||||
stm32h7_adc_disable(adc);
|
||||
stm32h7_adc_enter_pwr_down(adc);
|
||||
}
|
||||
|
||||
/**
|
||||
* stm32_adc_conf_scan_seq() - Build regular channels scan sequence
|
||||
* @indio_dev: IIO device
|
||||
|
|
@ -609,6 +1097,12 @@ static int stm32_adc_single_conv(struct iio_dev *indio_dev,
|
|||
|
||||
adc->bufi = 0;
|
||||
|
||||
if (adc->cfg->prepare) {
|
||||
ret = adc->cfg->prepare(adc);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* Program chan number in regular sequence (SQ1) */
|
||||
val = stm32_adc_readl(adc, regs->sqr[1].reg);
|
||||
val &= ~regs->sqr[1].mask;
|
||||
|
|
@ -640,6 +1134,9 @@ static int stm32_adc_single_conv(struct iio_dev *indio_dev,
|
|||
|
||||
stm32_adc_conv_irq_disable(adc);
|
||||
|
||||
if (adc->cfg->unprepare)
|
||||
adc->cfg->unprepare(adc);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
|
@ -864,10 +1361,16 @@ static int stm32_adc_buffer_postenable(struct iio_dev *indio_dev)
|
|||
struct stm32_adc *adc = iio_priv(indio_dev);
|
||||
int ret;
|
||||
|
||||
if (adc->cfg->prepare) {
|
||||
ret = adc->cfg->prepare(adc);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = stm32_adc_set_trig(indio_dev, indio_dev->trig);
|
||||
if (ret) {
|
||||
dev_err(&indio_dev->dev, "Can't set trigger\n");
|
||||
return ret;
|
||||
goto err_unprepare;
|
||||
}
|
||||
|
||||
ret = stm32_adc_dma_start(indio_dev);
|
||||
|
|
@ -895,6 +1398,9 @@ static int stm32_adc_buffer_postenable(struct iio_dev *indio_dev)
|
|||
dmaengine_terminate_all(adc->dma_chan);
|
||||
err_clr_trig:
|
||||
stm32_adc_set_trig(indio_dev, NULL);
|
||||
err_unprepare:
|
||||
if (adc->cfg->unprepare)
|
||||
adc->cfg->unprepare(adc);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
|
@ -918,6 +1424,9 @@ static int stm32_adc_buffer_predisable(struct iio_dev *indio_dev)
|
|||
if (stm32_adc_set_trig(indio_dev, NULL))
|
||||
dev_err(&indio_dev->dev, "Can't clear trigger\n");
|
||||
|
||||
if (adc->cfg->unprepare)
|
||||
adc->cfg->unprepare(adc);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
|
@ -1016,6 +1525,9 @@ static void stm32_adc_chan_init_one(struct iio_dev *indio_dev,
|
|||
chan->scan_type.realbits = adc->cfg->adc_info->resolutions[adc->res];
|
||||
chan->scan_type.storagebits = 16;
|
||||
chan->ext_info = stm32_adc_ext_info;
|
||||
|
||||
/* pre-build selected channels mask */
|
||||
adc->pcsel |= BIT(chan->channel);
|
||||
}
|
||||
|
||||
static int stm32_adc_chan_of_init(struct iio_dev *indio_dev)
|
||||
|
|
@ -1169,6 +1681,12 @@ static int stm32_adc_probe(struct platform_device *pdev)
|
|||
goto err_clk_disable;
|
||||
stm32_adc_set_res(adc);
|
||||
|
||||
if (adc->cfg->selfcalib) {
|
||||
ret = adc->cfg->selfcalib(adc);
|
||||
if (ret)
|
||||
goto err_clk_disable;
|
||||
}
|
||||
|
||||
ret = stm32_adc_chan_of_init(indio_dev);
|
||||
if (ret < 0)
|
||||
goto err_clk_disable;
|
||||
|
|
@ -1239,8 +1757,20 @@ static const struct stm32_adc_cfg stm32f4_adc_cfg = {
|
|||
.stop_conv = stm32f4_adc_stop_conv,
|
||||
};
|
||||
|
||||
static const struct stm32_adc_cfg stm32h7_adc_cfg = {
|
||||
.regs = &stm32h7_adc_regspec,
|
||||
.adc_info = &stm32h7_adc_info,
|
||||
.trigs = stm32h7_adc_trigs,
|
||||
.selfcalib = stm32h7_adc_selfcalib,
|
||||
.start_conv = stm32h7_adc_start_conv,
|
||||
.stop_conv = stm32h7_adc_stop_conv,
|
||||
.prepare = stm32h7_adc_prepare,
|
||||
.unprepare = stm32h7_adc_unprepare,
|
||||
};
|
||||
|
||||
static const struct of_device_id stm32_adc_of_match[] = {
|
||||
{ .compatible = "st,stm32f4-adc", .data = (void *)&stm32f4_adc_cfg },
|
||||
{ .compatible = "st,stm32h7-adc", .data = (void *)&stm32h7_adc_cfg },
|
||||
{},
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, stm32_adc_of_match);
|
||||
|
|
|
|||
Loading…
Reference in a new issue