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atl1c: clear PCIE error status in atl1c_reset_pcie
clear PCIE error status (error log is write-1-clear). REG_PCIE_UC_SEVERITY is removed as it's a standard pcie register, and using kernle API to access it. Signed-off-by: xiong <xiong@qca.qualcomm.com> Tested-by: Liu David <dwliu@qca.qualcomm.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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9c277d848d
commit
95f9aea769
2 changed files with 11 additions and 17 deletions
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@ -61,19 +61,6 @@ int atl1c_phy_power_saving(struct atl1c_hw *hw);
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#define LINK_CTRL_L1_EN 0x02
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#define LINK_CTRL_L1_EN 0x02
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#define LINK_CTRL_EXT_SYNC 0x80
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#define LINK_CTRL_EXT_SYNC 0x80
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#define REG_PCIE_UC_SEVERITY 0x10C
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#define PCIE_UC_SERVRITY_TRN 0x00000001
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#define PCIE_UC_SERVRITY_DLP 0x00000010
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#define PCIE_UC_SERVRITY_PSN_TLP 0x00001000
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#define PCIE_UC_SERVRITY_FCP 0x00002000
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#define PCIE_UC_SERVRITY_CPL_TO 0x00004000
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#define PCIE_UC_SERVRITY_CA 0x00008000
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#define PCIE_UC_SERVRITY_UC 0x00010000
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#define PCIE_UC_SERVRITY_ROV 0x00020000
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#define PCIE_UC_SERVRITY_MLFP 0x00040000
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#define PCIE_UC_SERVRITY_ECRC 0x00080000
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#define PCIE_UC_SERVRITY_UR 0x00100000
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#define REG_DEV_SERIALNUM_CTRL 0x200
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#define REG_DEV_SERIALNUM_CTRL 0x200
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#define REG_DEV_MAC_SEL_MASK 0x0 /* 0:EUI; 1:MAC */
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#define REG_DEV_MAC_SEL_MASK 0x0 /* 0:EUI; 1:MAC */
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#define REG_DEV_MAC_SEL_SHIFT 0
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#define REG_DEV_MAC_SEL_SHIFT 0
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@ -108,6 +108,7 @@ static void atl1c_reset_pcie(struct atl1c_hw *hw, u32 flag)
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u32 data;
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u32 data;
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u32 pci_cmd;
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u32 pci_cmd;
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struct pci_dev *pdev = hw->adapter->pdev;
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struct pci_dev *pdev = hw->adapter->pdev;
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int pos;
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AT_READ_REG(hw, PCI_COMMAND, &pci_cmd);
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AT_READ_REG(hw, PCI_COMMAND, &pci_cmd);
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pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
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pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
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@ -124,10 +125,16 @@ static void atl1c_reset_pcie(struct atl1c_hw *hw, u32 flag)
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/*
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/*
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* Mask some pcie error bits
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* Mask some pcie error bits
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*/
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*/
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AT_READ_REG(hw, REG_PCIE_UC_SEVERITY, &data);
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pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR);
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data &= ~PCIE_UC_SERVRITY_DLP;
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pci_read_config_dword(pdev, pos + PCI_ERR_UNCOR_SEVER, &data);
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data &= ~PCIE_UC_SERVRITY_FCP;
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data &= ~(PCI_ERR_UNC_DLP | PCI_ERR_UNC_FCP);
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AT_WRITE_REG(hw, REG_PCIE_UC_SEVERITY, data);
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pci_write_config_dword(pdev, pos + PCI_ERR_UNCOR_SEVER, data);
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/* clear error status */
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pci_write_config_word(pdev, pci_pcie_cap(pdev) + PCI_EXP_DEVSTA,
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PCI_EXP_DEVSTA_NFED |
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PCI_EXP_DEVSTA_FED |
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PCI_EXP_DEVSTA_CED |
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PCI_EXP_DEVSTA_URD);
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AT_READ_REG(hw, REG_LTSSM_ID_CTRL, &data);
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AT_READ_REG(hw, REG_LTSSM_ID_CTRL, &data);
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data &= ~LTSSM_ID_EN_WRO;
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data &= ~LTSSM_ID_EN_WRO;
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