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arm64: dts: ti: k3-j7200: Fix gic-v3 compatible regs
commit1a307cc299
upstream. Though GIC ARE option is disabled for no GIC-v2 compatibility, Cortex-A72 is free to implement the CPU interface as long as it communicates with the GIC using the stream protocol. This requires that the SoC integration mark out the PERIPHBASE[1] as reserved area within the SoC. See longer discussion in [2] for further information. Update the GIC register map to indicate offsets from PERIPHBASE based on [3]. Without doing this, systems like kvm will not function with gic-v2 emulation. [1] https://developer.arm.com/documentation/100095/0002/system-control/aarch64-register-descriptions/configuration-base-address-register--el1 [2] https://lore.kernel.org/all/87k0e0tirw.wl-maz@kernel.org/ [3] https://developer.arm.com/documentation/100095/0002/way1382452674438 Cc: stable@vger.kernel.org Fixes:d361ed8845
("arm64: dts: ti: Add support for J7200 SoC") Reported-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Nishanth Menon <nm@ti.com> Acked-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20220215201008.15235-4-nm@ti.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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2 changed files with 5 additions and 1 deletions
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@ -54,7 +54,10 @@ gic500: interrupt-controller@1800000 {
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
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<0x00 0x01900000 0x00 0x100000>; /* GICR */
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<0x00 0x01900000 0x00 0x100000>, /* GICR */
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<0x00 0x6f000000 0x00 0x2000>, /* GICC */
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<0x00 0x6f010000 0x00 0x1000>, /* GICH */
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<0x00 0x6f020000 0x00 0x2000>; /* GICV */
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/* vcpumntirq: virtual CPU interface maintenance interrupt */
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
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@ -127,6 +127,7 @@ cbass_main: bus@100000 {
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<0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* timesync router */
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<0x00 0x01000000 0x00 0x01000000 0x00 0x0d000000>, /* Most peripherals */
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<0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>, /* MAIN NAVSS */
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<0x00 0x6f000000 0x00 0x6f000000 0x00 0x00310000>, /* A72 PERIPHBASE */
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<0x00 0x70000000 0x00 0x70000000 0x00 0x00800000>, /* MSMC RAM */
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<0x00 0x18000000 0x00 0x18000000 0x00 0x08000000>, /* PCIe1 DAT0 */
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<0x41 0x00000000 0x41 0x00000000 0x01 0x00000000>, /* PCIe1 DAT1 */
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