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drm/amdgpu: move amdgpu_device_(vram|gtt)_location
Move that into amdgpu_gmc.c since we are really deadling with GMC address space here. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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8 changed files with 76 additions and 77 deletions
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@ -1166,10 +1166,6 @@ bool amdgpu_device_need_post(struct amdgpu_device *adev);
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void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes,
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void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes,
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u64 num_vis_bytes);
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u64 num_vis_bytes);
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void amdgpu_device_vram_location(struct amdgpu_device *adev,
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struct amdgpu_gmc *mc, u64 base);
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void amdgpu_device_gart_location(struct amdgpu_device *adev,
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struct amdgpu_gmc *mc);
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int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev);
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int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev);
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void amdgpu_device_program_register_sequence(struct amdgpu_device *adev,
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void amdgpu_device_program_register_sequence(struct amdgpu_device *adev,
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const u32 *registers,
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const u32 *registers,
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@ -651,71 +651,6 @@ void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb)
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__clear_bit(wb, adev->wb.used);
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__clear_bit(wb, adev->wb.used);
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}
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}
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/**
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* amdgpu_device_vram_location - try to find VRAM location
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*
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* @adev: amdgpu device structure holding all necessary informations
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* @mc: memory controller structure holding memory informations
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* @base: base address at which to put VRAM
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*
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* Function will try to place VRAM at base address provided
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* as parameter.
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*/
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void amdgpu_device_vram_location(struct amdgpu_device *adev,
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struct amdgpu_gmc *mc, u64 base)
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{
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uint64_t limit = (uint64_t)amdgpu_vram_limit << 20;
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mc->vram_start = base;
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mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
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if (limit && limit < mc->real_vram_size)
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mc->real_vram_size = limit;
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dev_info(adev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",
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mc->mc_vram_size >> 20, mc->vram_start,
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mc->vram_end, mc->real_vram_size >> 20);
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}
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/**
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* amdgpu_device_gart_location - try to find GART location
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*
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* @adev: amdgpu device structure holding all necessary informations
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* @mc: memory controller structure holding memory informations
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*
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* Function will place try to place GART before or after VRAM.
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*
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* If GART size is bigger than space left then we ajust GART size.
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* Thus function will never fails.
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*/
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void amdgpu_device_gart_location(struct amdgpu_device *adev,
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struct amdgpu_gmc *mc)
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{
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u64 size_af, size_bf;
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mc->gart_size += adev->pm.smu_prv_buffer_size;
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size_af = adev->gmc.mc_mask - mc->vram_end;
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size_bf = mc->vram_start;
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if (size_bf > size_af) {
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if (mc->gart_size > size_bf) {
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dev_warn(adev->dev, "limiting GART\n");
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mc->gart_size = size_bf;
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}
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mc->gart_start = 0;
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} else {
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if (mc->gart_size > size_af) {
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dev_warn(adev->dev, "limiting GART\n");
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mc->gart_size = size_af;
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}
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/* VCE doesn't like it when BOs cross a 4GB segment, so align
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* the GART base on a 4GB boundary as well.
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*/
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mc->gart_start = ALIGN(mc->vram_end + 1, 0x100000000ULL);
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}
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mc->gart_end = mc->gart_start + mc->gart_size - 1;
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dev_info(adev->dev, "GART: %lluM 0x%016llX - 0x%016llX\n",
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mc->gart_size >> 20, mc->gart_start, mc->gart_end);
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}
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/**
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/**
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* amdgpu_device_resize_fb_bar - try to resize FB BAR
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* amdgpu_device_resize_fb_bar - try to resize FB BAR
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*
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*
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@ -78,3 +78,67 @@ uint64_t amdgpu_gmc_pd_addr(struct amdgpu_bo *bo)
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}
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}
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return pd_addr;
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return pd_addr;
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}
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}
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/**
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* amdgpu_gmc_vram_location - try to find VRAM location
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*
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* @adev: amdgpu device structure holding all necessary informations
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* @mc: memory controller structure holding memory informations
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* @base: base address at which to put VRAM
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*
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* Function will try to place VRAM at base address provided
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* as parameter.
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*/
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void amdgpu_gmc_vram_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc,
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u64 base)
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{
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uint64_t limit = (uint64_t)amdgpu_vram_limit << 20;
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mc->vram_start = base;
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mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
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if (limit && limit < mc->real_vram_size)
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mc->real_vram_size = limit;
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dev_info(adev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",
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mc->mc_vram_size >> 20, mc->vram_start,
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mc->vram_end, mc->real_vram_size >> 20);
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}
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/**
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* amdgpu_gmc_gart_location - try to find GART location
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*
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* @adev: amdgpu device structure holding all necessary informations
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* @mc: memory controller structure holding memory informations
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*
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* Function will place try to place GART before or after VRAM.
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*
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* If GART size is bigger than space left then we ajust GART size.
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* Thus function will never fails.
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*/
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void amdgpu_gmc_gart_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc)
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{
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u64 size_af, size_bf;
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mc->gart_size += adev->pm.smu_prv_buffer_size;
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size_af = adev->gmc.mc_mask - mc->vram_end;
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size_bf = mc->vram_start;
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if (size_bf > size_af) {
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if (mc->gart_size > size_bf) {
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dev_warn(adev->dev, "limiting GART\n");
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mc->gart_size = size_bf;
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}
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mc->gart_start = 0;
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} else {
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if (mc->gart_size > size_af) {
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dev_warn(adev->dev, "limiting GART\n");
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mc->gart_size = size_af;
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}
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/* VCE doesn't like it when BOs cross a 4GB segment, so align
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* the GART base on a 4GB boundary as well.
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*/
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mc->gart_start = ALIGN(mc->vram_end + 1, 0x100000000ULL);
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}
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mc->gart_end = mc->gart_start + mc->gart_size - 1;
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dev_info(adev->dev, "GART: %lluM 0x%016llX - 0x%016llX\n",
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mc->gart_size >> 20, mc->gart_start, mc->gart_end);
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}
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@ -136,5 +136,9 @@ static inline bool amdgpu_gmc_vram_full_visible(struct amdgpu_gmc *gmc)
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void amdgpu_gmc_get_pde_for_bo(struct amdgpu_bo *bo, int level,
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void amdgpu_gmc_get_pde_for_bo(struct amdgpu_bo *bo, int level,
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uint64_t *addr, uint64_t *flags);
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uint64_t *addr, uint64_t *flags);
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uint64_t amdgpu_gmc_pd_addr(struct amdgpu_bo *bo);
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uint64_t amdgpu_gmc_pd_addr(struct amdgpu_bo *bo);
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void amdgpu_gmc_vram_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc,
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u64 base);
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void amdgpu_gmc_gart_location(struct amdgpu_device *adev,
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struct amdgpu_gmc *mc);
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#endif
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#endif
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@ -224,8 +224,8 @@ static void gmc_v6_0_vram_gtt_location(struct amdgpu_device *adev,
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u64 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF;
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u64 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF;
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base <<= 24;
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base <<= 24;
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amdgpu_device_vram_location(adev, &adev->gmc, base);
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amdgpu_gmc_vram_location(adev, &adev->gmc, base);
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amdgpu_device_gart_location(adev, mc);
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amdgpu_gmc_gart_location(adev, mc);
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}
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}
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static void gmc_v6_0_mc_program(struct amdgpu_device *adev)
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static void gmc_v6_0_mc_program(struct amdgpu_device *adev)
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@ -242,8 +242,8 @@ static void gmc_v7_0_vram_gtt_location(struct amdgpu_device *adev,
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u64 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF;
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u64 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF;
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base <<= 24;
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base <<= 24;
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amdgpu_device_vram_location(adev, &adev->gmc, base);
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amdgpu_gmc_vram_location(adev, &adev->gmc, base);
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amdgpu_device_gart_location(adev, mc);
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amdgpu_gmc_gart_location(adev, mc);
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}
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}
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/**
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/**
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@ -411,8 +411,8 @@ static void gmc_v8_0_vram_gtt_location(struct amdgpu_device *adev,
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base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF;
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base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF;
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base <<= 24;
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base <<= 24;
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amdgpu_device_vram_location(adev, &adev->gmc, base);
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amdgpu_gmc_vram_location(adev, &adev->gmc, base);
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amdgpu_device_gart_location(adev, mc);
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amdgpu_gmc_gart_location(adev, mc);
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}
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}
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/**
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/**
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@ -749,8 +749,8 @@ static void gmc_v9_0_vram_gtt_location(struct amdgpu_device *adev,
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u64 base = 0;
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u64 base = 0;
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if (!amdgpu_sriov_vf(adev))
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if (!amdgpu_sriov_vf(adev))
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base = mmhub_v1_0_get_fb_location(adev);
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base = mmhub_v1_0_get_fb_location(adev);
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amdgpu_device_vram_location(adev, &adev->gmc, base);
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amdgpu_gmc_vram_location(adev, &adev->gmc, base);
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amdgpu_device_gart_location(adev, mc);
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amdgpu_gmc_gart_location(adev, mc);
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/* base offset of vram pages */
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/* base offset of vram pages */
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adev->vm_manager.vram_base_offset = gfxhub_v1_0_get_mc_fb_offset(adev);
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adev->vm_manager.vram_base_offset = gfxhub_v1_0_get_mc_fb_offset(adev);
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}
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}
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