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[MIPS] All MIPS32 processors support64-bit physical addresses.
Still, only the 4K may actually implement it. Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
parent
0bfa130e74
commit
962f480e0f
5 changed files with 10 additions and 10 deletions
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@ -142,7 +142,7 @@ void *kmap_coherent(struct page *page, unsigned long addr)
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#endif
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vaddr = __fix_to_virt(FIX_CMAP_END - idx);
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pte = mk_pte(page, PAGE_KERNEL);
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#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1)
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#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
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entrylo = pte.pte_high;
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#else
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entrylo = pte_val(pte) >> 6;
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@ -299,7 +299,7 @@ void __update_tlb(struct vm_area_struct * vma, unsigned long address, pte_t pte)
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idx = read_c0_index();
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ptep = pte_offset_map(pmdp, address);
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#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1)
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#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
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write_c0_entrylo0(ptep->pte_high);
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ptep++;
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write_c0_entrylo1(ptep->pte_high);
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@ -107,7 +107,7 @@ static inline void pmd_clear(pmd_t *pmdp)
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pmd_val(*pmdp) = ((unsigned long) invalid_pte_table);
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}
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#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1)
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#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
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#define pte_page(x) pfn_to_page(pte_pfn(x))
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#define pte_pfn(x) ((unsigned long)((x).pte_high >> 6))
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static inline pte_t
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@ -130,7 +130,7 @@ pfn_pte(unsigned long pfn, pgprot_t prot)
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#define pte_pfn(x) ((unsigned long)((x).pte >> PAGE_SHIFT))
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#define pfn_pte(pfn, prot) __pte(((unsigned long long)(pfn) << PAGE_SHIFT) | pgprot_val(prot))
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#endif
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#endif /* defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1) */
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#endif /* defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) */
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#define __pgd_offset(address) pgd_index(address)
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#define __pud_offset(address) (((address) >> PUD_SHIFT) & (PTRS_PER_PUD-1))
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@ -32,7 +32,7 @@
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* unpredictable things. The code (when it is written) to deal with
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* this problem will be in the update_mmu_cache() code for the r4k.
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*/
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#if defined(CONFIG_CPU_MIPS32_R1) && defined(CONFIG_64BIT_PHYS_ADDR)
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#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
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#define _PAGE_PRESENT (1<<6) /* implemented in software */
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#define _PAGE_READ (1<<7) /* implemented in software */
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@ -122,7 +122,7 @@
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#endif
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#endif
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#endif /* defined(CONFIG_CPU_MIPS32_R1) && defined(CONFIG_64BIT_PHYS_ADDR) */
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#endif /* defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) */
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#define __READABLE (_PAGE_READ | _PAGE_SILENT_READ | _PAGE_ACCESSED)
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#define __WRITEABLE (_PAGE_WRITE | _PAGE_SILENT_WRITE | _PAGE_MODIFIED)
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@ -139,7 +139,7 @@
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#define PAGE_CACHABLE_DEFAULT _CACHE_CACHABLE_COW
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#endif
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#if defined(CONFIG_CPU_MIPS32_R1) && defined(CONFIG_64BIT_PHYS_ADDR)
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#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
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#define CONF_CM_DEFAULT (PAGE_CACHABLE_DEFAULT >> 3)
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#else
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#define CONF_CM_DEFAULT (PAGE_CACHABLE_DEFAULT >> 9)
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@ -79,7 +79,7 @@ extern void paging_init(void);
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#define pmd_page(pmd) (pfn_to_page(pmd_phys(pmd) >> PAGE_SHIFT))
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#define pmd_page_vaddr(pmd) pmd_val(pmd)
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#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1)
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#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
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#define pte_none(pte) (!(((pte).pte_low | (pte).pte_high) & ~_PAGE_GLOBAL))
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#define pte_present(pte) ((pte).pte_low & _PAGE_PRESENT)
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@ -182,7 +182,7 @@ extern pgd_t swapper_pg_dir[];
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* The following only work if pte_present() is true.
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* Undefined behaviour if not..
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*/
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#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1)
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#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
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static inline int pte_write(pte_t pte) { return pte.pte_low & _PAGE_WRITE; }
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static inline int pte_dirty(pte_t pte) { return pte.pte_low & _PAGE_MODIFIED; }
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static inline int pte_young(pte_t pte) { return pte.pte_low & _PAGE_ACCESSED; }
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@ -309,7 +309,7 @@ static inline pgprot_t pgprot_noncached(pgprot_t _prot)
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*/
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#define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot))
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#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1)
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#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
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static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
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{
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pte.pte_low &= _PAGE_CHG_MASK;
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