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arm64: cpufeatures: Check ICC_EL1_SRE.SRE before enabling ARM64_HAS_SYSREG_GIC_CPUIF
As the firmware (or the hypervisor) may have disabled SRE access, check that SRE can actually be enabled before declaring that we do have that capability. Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
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1 changed files with 18 additions and 1 deletions
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@ -23,6 +23,8 @@
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#include <asm/cpufeature.h>
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#include <asm/processor.h>
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#include <linux/irqchip/arm-gic-v3.h>
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static bool
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feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry)
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{
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@ -45,11 +47,26 @@ __ID_FEAT_CHK(id_aa64pfr0);
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__ID_FEAT_CHK(id_aa64mmfr1);
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__ID_FEAT_CHK(id_aa64isar0);
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static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry)
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{
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bool has_sre;
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if (!has_id_aa64pfr0_feature(entry))
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return false;
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has_sre = gic_enable_sre();
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if (!has_sre)
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pr_warn_once("%s present but disabled by higher exception level\n",
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entry->desc);
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return has_sre;
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}
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static const struct arm64_cpu_capabilities arm64_features[] = {
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{
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.desc = "GIC system register CPU interface",
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.capability = ARM64_HAS_SYSREG_GIC_CPUIF,
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.matches = has_id_aa64pfr0_feature,
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.matches = has_useable_gicv3_cpuif,
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.field_pos = 24,
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.min_field_value = 1,
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},
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