ARM: dts: imx6dl-colibri: Cleanup
- Sort pinctrl nodes alphabetically - End all pinctrl node names in grp and avoid using dashes - Change pinctrl_usbc_id_1's node name to not use underscores - Change the pmic's node name to pmic@8 per binding requirement - Add sound-dai-cells to the codec node per binding requirement Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This commit is contained in:
Max Krummenacher
Shawn Guo
parent
1524b27c94
commit
965f2ca42c
|
|
@ -46,10 +46,10 @@
|
|||
|
||||
mcp251x0: mcp251x@0 {
|
||||
compatible = "microchip,mcp2515";
|
||||
reg = <0>;
|
||||
clocks = <&clk16m>;
|
||||
interrupt-parent = <&gpio3>;
|
||||
interrupts = <27 0x2>;
|
||||
reg = <0>;
|
||||
spi-max-frequency = <10000000>;
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -104,36 +104,36 @@
|
|||
|
||||
reg_usb_host_vbus: regulator-usb-host-vbus {
|
||||
compatible = "regulator-fixed";
|
||||
gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>; /* USBH_PEN */
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_regulator_usbh_pwr>;
|
||||
regulator-name = "usb_host_vbus";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>; /* USBH_PEN */
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-name = "usb_host_vbus";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sound {
|
||||
compatible = "fsl,imx-audio-sgtl5000";
|
||||
model = "imx6dl-colibri-sgtl5000";
|
||||
ssi-controller = <&ssi1>;
|
||||
audio-codec = <&codec>;
|
||||
audio-routing =
|
||||
"Headphone Jack", "HP_OUT",
|
||||
"LINE_IN", "Line In Jack",
|
||||
"MIC_IN", "Mic Jack",
|
||||
"Mic Jack", "Mic Bias";
|
||||
model = "imx6dl-colibri-sgtl5000";
|
||||
mux-int-port = <1>;
|
||||
mux-ext-port = <5>;
|
||||
ssi-controller = <&ssi1>;
|
||||
};
|
||||
|
||||
/* Optional S/PDIF in on SODIMM 88 and out on SODIMM 90, 137 or 168 */
|
||||
sound_spdif: sound-spdif {
|
||||
compatible = "fsl,imx-audio-spdif";
|
||||
model = "imx-spdif";
|
||||
spdif-controller = <&spdif>;
|
||||
spdif-in;
|
||||
spdif-out;
|
||||
model = "imx-spdif";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
|
@ -171,10 +171,10 @@
|
|||
};
|
||||
|
||||
&fec {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_enet>;
|
||||
phy-mode = "rmii";
|
||||
phy-handle = <ðphy>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_enet>;
|
||||
status = "okay";
|
||||
|
||||
mdio {
|
||||
|
|
@ -425,61 +425,61 @@
|
|||
sda-gpios = <&gpio3 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
|
||||
status = "okay";
|
||||
|
||||
pmic: pfuze100@8 {
|
||||
pmic: pmic@8 {
|
||||
compatible = "fsl,pfuze100";
|
||||
fsl,pmic-stby-poweroff;
|
||||
reg = <0x08>;
|
||||
|
||||
regulators {
|
||||
sw1a_reg: sw1ab {
|
||||
regulator-min-microvolt = <300000>;
|
||||
regulator-max-microvolt = <1875000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-max-microvolt = <1875000>;
|
||||
regulator-min-microvolt = <300000>;
|
||||
regulator-ramp-delay = <6250>;
|
||||
};
|
||||
|
||||
sw1c_reg: sw1c {
|
||||
regulator-min-microvolt = <300000>;
|
||||
regulator-max-microvolt = <1875000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-max-microvolt = <1875000>;
|
||||
regulator-min-microvolt = <300000>;
|
||||
regulator-ramp-delay = <6250>;
|
||||
};
|
||||
|
||||
sw3a_reg: sw3a {
|
||||
regulator-min-microvolt = <400000>;
|
||||
regulator-max-microvolt = <1975000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-max-microvolt = <1975000>;
|
||||
regulator-min-microvolt = <400000>;
|
||||
};
|
||||
|
||||
swbst_reg: swbst {
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5150000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-max-microvolt = <5150000>;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
};
|
||||
|
||||
snvs_reg: vsnvs {
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
regulator-min-microvolt = <1000000>;
|
||||
};
|
||||
|
||||
vref_reg: vrefddr {
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
/* vgen1: unused */
|
||||
|
||||
vgen2_reg: vgen2 {
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <1550000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-max-microvolt = <1550000>;
|
||||
regulator-min-microvolt = <800000>;
|
||||
};
|
||||
|
||||
/*
|
||||
|
|
@ -487,57 +487,58 @@
|
|||
* the i.MX 6 NVCC_SD1.
|
||||
*/
|
||||
vgen3_reg: vgen3 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
};
|
||||
|
||||
vgen4_reg: vgen4 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
};
|
||||
|
||||
vgen5_reg: vgen5 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
};
|
||||
|
||||
vgen6_reg: vgen6 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
codec: sgtl5000@a {
|
||||
compatible = "fsl,sgtl5000";
|
||||
reg = <0x0a>;
|
||||
clocks = <&clks IMX6QDL_CLK_CKO>;
|
||||
lrclk-strength = <3>;
|
||||
reg = <0x0a>;
|
||||
#sound-dai-cells = <0>;
|
||||
VDDA-supply = <®_module_3v3_audio>;
|
||||
VDDIO-supply = <®_module_3v3>;
|
||||
VDDD-supply = <&vgen4_reg>;
|
||||
lrclk-strength = <3>;
|
||||
};
|
||||
|
||||
/* STMPE811 touch screen controller */
|
||||
stmpe811@41 {
|
||||
compatible = "st,stmpe811";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_touch_int>;
|
||||
reg = <0x41>;
|
||||
blocks = <0x5>;
|
||||
interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
|
||||
interrupt-parent = <&gpio6>;
|
||||
interrupt-controller;
|
||||
id = <0>;
|
||||
blocks = <0x5>;
|
||||
irq-trigger = <0x1>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_touch_int>;
|
||||
reg = <0x41>;
|
||||
/* 3.25 MHz ADC clock speed */
|
||||
st,adc-freq = <1>;
|
||||
/* 12-bit ADC */
|
||||
|
|
@ -643,27 +644,27 @@
|
|||
|
||||
/* Colibri UART_A */
|
||||
&uart1 {
|
||||
fsl,dte-mode;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart1_dte &pinctrl_uart1_ctrl>;
|
||||
fsl,dte-mode;
|
||||
uart-has-rtscts;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
/* Colibri UART_B */
|
||||
&uart2 {
|
||||
fsl,dte-mode;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart2_dte>;
|
||||
fsl,dte-mode;
|
||||
uart-has-rtscts;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
/* Colibri UART_C */
|
||||
&uart3 {
|
||||
fsl,dte-mode;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart3_dte>;
|
||||
fsl,dte-mode;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -675,27 +676,27 @@
|
|||
|
||||
/* Colibri MMC */
|
||||
&usdhc1 {
|
||||
cd-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; /* MMCD */
|
||||
bus-width = <4>;
|
||||
no-1-8-v;
|
||||
disable-wp;
|
||||
pinctrl-names = "default", "state_100mhz", "state_200mhz";
|
||||
pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_mmc_cd>;
|
||||
pinctrl-1 = <&pinctrl_usdhc1_100mhz &pinctrl_mmc_cd>;
|
||||
pinctrl-2 = <&pinctrl_usdhc1_200mhz &pinctrl_mmc_cd>;
|
||||
cd-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; /* MMCD */
|
||||
disable-wp;
|
||||
vmmc-supply = <®_module_3v3>;
|
||||
vqmmc-supply = <&vgen3_reg>;
|
||||
bus-width = <4>;
|
||||
no-1-8-v;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
/* eMMC */
|
||||
&usdhc3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usdhc3>;
|
||||
vqmmc-supply = <®_module_3v3>;
|
||||
bus-width = <8>;
|
||||
no-1-8-v;
|
||||
non-removable;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usdhc3>;
|
||||
vqmmc-supply = <®_module_3v3>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
|
@ -737,12 +738,12 @@
|
|||
|
||||
pinctrl_audmux: audmuxgrp {
|
||||
fsl,pins = <
|
||||
/* SGTL5000 sys_mclk */
|
||||
MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0
|
||||
MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x130b0
|
||||
MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x130b0
|
||||
MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x130b0
|
||||
MX6QDL_PAD_KEY_ROW1__AUD5_RXD 0x130b0
|
||||
/* SGTL5000 sys_mclk */
|
||||
MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0
|
||||
>;
|
||||
};
|
||||
|
||||
|
|
@ -779,26 +780,26 @@
|
|||
|
||||
pinctrl_ecspi4: ecspi4grp {
|
||||
fsl,pins = <
|
||||
/* SPI CS */
|
||||
MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x000b1
|
||||
MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1
|
||||
MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1
|
||||
MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1
|
||||
/* SPI CS */
|
||||
MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x000b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_enet: enetgrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0
|
||||
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
|
||||
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
|
||||
MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0
|
||||
MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0
|
||||
MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0
|
||||
MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0
|
||||
MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
|
||||
MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0
|
||||
MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0
|
||||
MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0
|
||||
MX6QDL_PAD_GPIO_16__ENET_REF_CLK ((1<<30) | 0x1b0b0)
|
||||
MX6QDL_PAD_GPIO_16__ENET_REF_CLK ((1<<30) | 0x1b0b0)
|
||||
>;
|
||||
};
|
||||
|
||||
|
|
@ -835,13 +836,13 @@
|
|||
>;
|
||||
};
|
||||
|
||||
pinctrl_gpio_bl_on: gpioblon {
|
||||
pinctrl_gpio_bl_on: gpioblongrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x1b0b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_gpio_keys: gpiokeys {
|
||||
pinctrl_gpio_keys: gpiokeysgrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x130b0
|
||||
>;
|
||||
|
|
@ -856,15 +857,15 @@
|
|||
|
||||
pinctrl_i2c2: i2c2grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
|
||||
MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1
|
||||
MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c2_gpio: i2c2gpiogrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x4001b8b1
|
||||
MX6QDL_PAD_EIM_D16__GPIO3_IO16 0x4001b8b1
|
||||
MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x4001b8b1
|
||||
>;
|
||||
};
|
||||
|
||||
|
|
@ -896,8 +897,8 @@
|
|||
MX6QDL_PAD_EIM_EB3__IPU1_CSI1_HSYNC 0xb0b1
|
||||
MX6QDL_PAD_EIM_D29__IPU1_CSI1_VSYNC 0xb0b1
|
||||
/* Disable PWM pins on camera interface */
|
||||
MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x40
|
||||
MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x40
|
||||
MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x40
|
||||
>;
|
||||
};
|
||||
|
||||
|
|
@ -937,14 +938,14 @@
|
|||
>;
|
||||
};
|
||||
|
||||
pinctrl_mic_gnd: gpiomicgnd {
|
||||
pinctrl_mic_gnd: micgndgrp {
|
||||
fsl,pins = <
|
||||
/* Controls Mic GND, PU or '1' pull Mic GND to GND */
|
||||
MX6QDL_PAD_RGMII_TD1__GPIO6_IO21 0x1b0b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_mmc_cd: gpiommccd {
|
||||
pinctrl_mmc_cd: mmccdgrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x1b0b1
|
||||
>;
|
||||
|
|
@ -958,15 +959,15 @@
|
|||
|
||||
pinctrl_pwm2: pwm2grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1
|
||||
MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x00040
|
||||
MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pwm3: pwm3grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
|
||||
MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x00040
|
||||
MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
|
||||
>;
|
||||
};
|
||||
|
||||
|
|
@ -983,13 +984,6 @@
|
|||
>;
|
||||
};
|
||||
|
||||
pinctrl_usbh_oc_1: usbhoc1grp {
|
||||
fsl,pins = <
|
||||
/* USBH_OC */
|
||||
MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x1b0b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_spdif: spdifgrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0
|
||||
|
|
@ -1032,9 +1026,9 @@
|
|||
pinctrl_uart2_dte: uart2dtegrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD4_DAT4__UART2_TX_DATA 0x1b0b1
|
||||
MX6QDL_PAD_SD4_DAT7__UART2_RX_DATA 0x1b0b1
|
||||
MX6QDL_PAD_SD4_DAT6__UART2_RTS_B 0x1b0b1
|
||||
MX6QDL_PAD_SD4_DAT5__UART2_CTS_B 0x1b0b1
|
||||
MX6QDL_PAD_SD4_DAT6__UART2_RTS_B 0x1b0b1
|
||||
MX6QDL_PAD_SD4_DAT7__UART2_RX_DATA 0x1b0b1
|
||||
>;
|
||||
};
|
||||
|
||||
|
|
@ -1049,20 +1043,27 @@
|
|||
fsl,pins = <
|
||||
/* USBC_DET */
|
||||
MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0
|
||||
/* USBC_DET_EN */
|
||||
MX6QDL_PAD_RGMII_TX_CTL__GPIO6_IO26 0x0f058
|
||||
/* USBC_DET_OVERWRITE */
|
||||
MX6QDL_PAD_RGMII_RXC__GPIO6_IO30 0x0f058
|
||||
/* USBC_DET_EN */
|
||||
MX6QDL_PAD_RGMII_TX_CTL__GPIO6_IO26 0x0f058
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usbc_id_1: usbc_id-1 {
|
||||
pinctrl_usbc_id_1: usbcid1grp {
|
||||
fsl,pins = <
|
||||
/* USBC_ID */
|
||||
MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usbh_oc_1: usbhoc1grp {
|
||||
fsl,pins = <
|
||||
/* USBH_OC */
|
||||
MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x1b0b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc1: usdhc1grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17071
|
||||
|
|
@ -1074,7 +1075,7 @@
|
|||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
|
||||
pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170b1
|
||||
MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100b1
|
||||
|
|
@ -1085,7 +1086,7 @@
|
|||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
|
||||
pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170f1
|
||||
MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100f1
|
||||
|
|
@ -1134,13 +1135,93 @@
|
|||
>;
|
||||
};
|
||||
|
||||
/* ADDRESS[16:18] [25] used as GPIO */
|
||||
pinctrl_weim_gpio_1: weimgpio1grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x1b0b0
|
||||
MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x1b0b0
|
||||
MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x1b0b0
|
||||
MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x1b0b0
|
||||
MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x1b0b0
|
||||
MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x1b0b0
|
||||
MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0
|
||||
MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
|
||||
MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0
|
||||
MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0
|
||||
>;
|
||||
};
|
||||
|
||||
/* ADDRESS[19:24] used as GPIO */
|
||||
pinctrl_weim_gpio_2: weimgpio2grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x1b0b0
|
||||
MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x1b0b0
|
||||
MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x1b0b0
|
||||
MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x1b0b0
|
||||
MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x1b0b0
|
||||
MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x1b0b0
|
||||
MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0
|
||||
MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0
|
||||
MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0
|
||||
>;
|
||||
};
|
||||
|
||||
/* DATA[16:31] used as GPIO */
|
||||
pinctrl_weim_gpio_3: weimgpio3grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19 0x1b0b0
|
||||
MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x1b0b0
|
||||
MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x1b0b0
|
||||
MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x1b0b0
|
||||
MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0
|
||||
MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0
|
||||
MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b0
|
||||
MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0
|
||||
MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x1b0b0
|
||||
MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x1b0b0
|
||||
MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x1b0b0
|
||||
MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x1b0b0
|
||||
MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x1b0b0
|
||||
MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x1b0b0
|
||||
MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x1b0b0
|
||||
>;
|
||||
};
|
||||
|
||||
/* DQM[0:3] used as GPIO */
|
||||
pinctrl_weim_gpio_4: weimgpio4grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x1b0b0
|
||||
MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x1b0b0
|
||||
MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0
|
||||
MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x1b0b0
|
||||
>;
|
||||
};
|
||||
|
||||
/* RDY used as GPIO */
|
||||
pinctrl_weim_gpio_5: weimgpio5grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x1b0b0
|
||||
>;
|
||||
};
|
||||
|
||||
/* ADDRESS[16] DATA[30] used as GPIO */
|
||||
pinctrl_weim_gpio_6: weimgpio6grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0
|
||||
MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_weim_npwe: weimnpwegrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_RGMII_TD2__GPIO6_IO22 0x130b0
|
||||
MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x0040
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_weim_sram: weimsramgrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0b1
|
||||
MX6QDL_PAD_EIM_RW__EIM_RW 0xb0b1
|
||||
/* Data */
|
||||
MX6QDL_PAD_CSI0_DATA_EN__EIM_DATA00 0x1b0b0
|
||||
MX6QDL_PAD_CSI0_VSYNC__EIM_DATA01 0x1b0b0
|
||||
MX6QDL_PAD_CSI0_DAT4__EIM_DATA02 0x1b0b0
|
||||
MX6QDL_PAD_CSI0_DAT5__EIM_DATA03 0x1b0b0
|
||||
MX6QDL_PAD_CSI0_DAT6__EIM_DATA04 0x1b0b0
|
||||
|
|
@ -1155,114 +1236,35 @@
|
|||
MX6QDL_PAD_CSI0_DAT17__EIM_DATA13 0x1b0b0
|
||||
MX6QDL_PAD_CSI0_DAT18__EIM_DATA14 0x1b0b0
|
||||
MX6QDL_PAD_CSI0_DAT19__EIM_DATA15 0x1b0b0
|
||||
MX6QDL_PAD_CSI0_DATA_EN__EIM_DATA00 0x1b0b0
|
||||
MX6QDL_PAD_CSI0_VSYNC__EIM_DATA01 0x1b0b0
|
||||
/* Address */
|
||||
MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0b1
|
||||
MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0b1
|
||||
MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0b1
|
||||
MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0b1
|
||||
MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0b1
|
||||
MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0b1
|
||||
MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0b1
|
||||
MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0b1
|
||||
MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0b1
|
||||
MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0b1
|
||||
MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0b1
|
||||
MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0b1
|
||||
MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0b1
|
||||
MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0b1
|
||||
MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0b1
|
||||
MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0b1
|
||||
MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0b1
|
||||
MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0b1
|
||||
MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0b1
|
||||
MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0b1
|
||||
MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0b1
|
||||
MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0b1
|
||||
MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0b1
|
||||
MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0b1
|
||||
MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0b1
|
||||
MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0b1
|
||||
MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0b1
|
||||
MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0b1
|
||||
MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0b1
|
||||
MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0b1
|
||||
MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0b1
|
||||
/* Ctrl */
|
||||
MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0b1
|
||||
MX6QDL_PAD_EIM_RW__EIM_RW 0xb0b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_weim_rdnwr: weimrdnwr {
|
||||
pinctrl_weim_rdnwr: weimrdnwrgrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD2_CLK__GPIO1_IO10 0x0040
|
||||
MX6QDL_PAD_RGMII_TD3__GPIO6_IO23 0x130b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_weim_npwe: weimnpwe {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x0040
|
||||
MX6QDL_PAD_RGMII_TD2__GPIO6_IO22 0x130b0
|
||||
>;
|
||||
};
|
||||
|
||||
/* ADDRESS[16:18] [25] used as GPIO */
|
||||
pinctrl_weim_gpio_1: weimgpio-1 {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
|
||||
MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0
|
||||
MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0
|
||||
MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x1b0b0
|
||||
MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x1b0b0
|
||||
MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x1b0b0
|
||||
MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x1b0b0
|
||||
MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x1b0b0
|
||||
MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x1b0b0
|
||||
MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0
|
||||
>;
|
||||
};
|
||||
|
||||
/* ADDRESS[19:24] used as GPIO */
|
||||
pinctrl_weim_gpio_2: weimgpio-2 {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0
|
||||
MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0
|
||||
MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x1b0b0
|
||||
MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x1b0b0
|
||||
MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x1b0b0
|
||||
MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x1b0b0
|
||||
MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x1b0b0
|
||||
MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x1b0b0
|
||||
MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0
|
||||
>;
|
||||
};
|
||||
|
||||
/* DATA[16:31] used as GPIO */
|
||||
pinctrl_weim_gpio_3: weimgpio-3 {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x1b0b0
|
||||
MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x1b0b0
|
||||
MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x1b0b0
|
||||
MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x1b0b0
|
||||
MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x1b0b0
|
||||
MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x1b0b0
|
||||
MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x1b0b0
|
||||
MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x1b0b0
|
||||
MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x1b0b0
|
||||
MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0
|
||||
MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19 0x1b0b0
|
||||
MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x1b0b0
|
||||
MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0
|
||||
MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b0
|
||||
MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0
|
||||
>;
|
||||
};
|
||||
|
||||
/* DQM[0:3] used as GPIO */
|
||||
pinctrl_weim_gpio_4: weimgpio-4 {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x1b0b0
|
||||
MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x1b0b0
|
||||
MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x1b0b0
|
||||
MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0
|
||||
>;
|
||||
};
|
||||
|
||||
/* RDY used as GPIO */
|
||||
pinctrl_weim_gpio_5: weimgpio-5 {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x1b0b0
|
||||
>;
|
||||
};
|
||||
|
||||
/* ADDRESS[16] DATA[30] used as GPIO */
|
||||
pinctrl_weim_gpio_6: weimgpio-6 {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
|
||||
MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0
|
||||
MX6QDL_PAD_SD2_CLK__GPIO1_IO10 0x0040
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
Loading…
Reference in New Issue