[IA64] Add API for allocating Dynamic TR resource.
Dynamic TR resource should be managed in the uniform way. Add two interfaces for kernel: ia64_itr_entry: Allocate a (pair of) TR for caller. ia64_ptr_entry: Purge a (pair of ) TR by caller. Signed-off-by: Xiantao Zhang <xiantao.zhang@intel.com> Signed-off-by: Anthony Xu <anthony.xu@intel.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
This commit is contained in:
Xiantao Zhang
Tony Luck
parent
9597362d35
commit
96651896b8
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@ -97,6 +97,7 @@
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#include <asm/irq.h>
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#include <asm/hw_irq.h>
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#include <asm/tlb.h>
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#include "mca_drv.h"
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#include "entry.h"
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@ -112,6 +113,7 @@ DEFINE_PER_CPU(u64, ia64_mca_data); /* == __per_cpu_mca[smp_processor_id()] */
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DEFINE_PER_CPU(u64, ia64_mca_per_cpu_pte); /* PTE to map per-CPU area */
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DEFINE_PER_CPU(u64, ia64_mca_pal_pte); /* PTE to map PAL code */
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DEFINE_PER_CPU(u64, ia64_mca_pal_base); /* vaddr PAL code granule */
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DEFINE_PER_CPU(u64, ia64_mca_tr_reload); /* Flag for TR reload */
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unsigned long __per_cpu_mca[NR_CPUS];
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@ -1182,6 +1184,49 @@ all_in:
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return;
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}
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/* mca_insert_tr
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*
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* Switch rid when TR reload and needed!
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* iord: 1: itr, 2: itr;
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*
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*/
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static void mca_insert_tr(u64 iord)
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{
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int i;
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u64 old_rr;
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struct ia64_tr_entry *p;
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unsigned long psr;
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int cpu = smp_processor_id();
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psr = ia64_clear_ic();
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for (i = IA64_TR_ALLOC_BASE; i < IA64_TR_ALLOC_MAX; i++) {
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p = &__per_cpu_idtrs[cpu][iord-1][i];
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if (p->pte & 0x1) {
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old_rr = ia64_get_rr(p->ifa);
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if (old_rr != p->rr) {
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ia64_set_rr(p->ifa, p->rr);
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ia64_srlz_d();
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}
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ia64_ptr(iord, p->ifa, p->itir >> 2);
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ia64_srlz_i();
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if (iord & 0x1) {
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ia64_itr(0x1, i, p->ifa, p->pte, p->itir >> 2);
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ia64_srlz_i();
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}
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if (iord & 0x2) {
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ia64_itr(0x2, i, p->ifa, p->pte, p->itir >> 2);
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ia64_srlz_i();
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}
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if (old_rr != p->rr) {
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ia64_set_rr(p->ifa, old_rr);
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ia64_srlz_d();
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}
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}
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}
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ia64_set_psr(psr);
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}
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/*
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* ia64_mca_handler
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*
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@ -1271,6 +1316,10 @@ ia64_mca_handler(struct pt_regs *regs, struct switch_stack *sw,
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monarch_cpu = -1;
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#endif
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}
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if (__get_cpu_var(ia64_mca_tr_reload)) {
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mca_insert_tr(0x1); /*Reload dynamic itrs*/
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mca_insert_tr(0x2); /*Reload dynamic itrs*/
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}
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if (notify_die(DIE_MCA_MONARCH_LEAVE, "MCA", regs, (long)&nd, 0, recover)
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== NOTIFY_STOP)
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ia64_mca_spin(__func__);
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@ -219,8 +219,13 @@ ia64_reload_tr:
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mov r20=IA64_TR_CURRENT_STACK
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;;
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itr.d dtr[r20]=r16
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GET_THIS_PADDR(r2, ia64_mca_tr_reload)
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mov r18 = 1
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;;
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srlz.d
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;;
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st8 [r2] =r18
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;;
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done_tlb_purge_and_reload:
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@ -26,6 +26,8 @@
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#include <asm/pal.h>
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#include <asm/tlbflush.h>
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#include <asm/dma.h>
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#include <asm/processor.h>
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#include <asm/tlb.h>
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static struct {
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unsigned long mask; /* mask of supported purge page-sizes */
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@ -39,6 +41,10 @@ struct ia64_ctx ia64_ctx = {
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};
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DEFINE_PER_CPU(u8, ia64_need_tlb_flush);
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DEFINE_PER_CPU(u8, ia64_tr_num); /*Number of TR slots in current processor*/
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DEFINE_PER_CPU(u8, ia64_tr_used); /*Max Slot number used by kernel*/
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struct ia64_tr_entry __per_cpu_idtrs[NR_CPUS][2][IA64_TR_ALLOC_MAX];
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/*
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* Initializes the ia64_ctx.bitmap array based on max_ctx+1.
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@ -190,6 +196,9 @@ ia64_tlb_init (void)
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ia64_ptce_info_t uninitialized_var(ptce_info); /* GCC be quiet */
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unsigned long tr_pgbits;
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long status;
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pal_vm_info_1_u_t vm_info_1;
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pal_vm_info_2_u_t vm_info_2;
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int cpu = smp_processor_id();
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if ((status = ia64_pal_vm_page_size(&tr_pgbits, &purge.mask)) != 0) {
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printk(KERN_ERR "PAL_VM_PAGE_SIZE failed with status=%ld; "
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@ -206,4 +215,191 @@ ia64_tlb_init (void)
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local_cpu_data->ptce_stride[1] = ptce_info.stride[1];
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local_flush_tlb_all(); /* nuke left overs from bootstrapping... */
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status = ia64_pal_vm_summary(&vm_info_1, &vm_info_2);
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if (status) {
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printk(KERN_ERR "ia64_pal_vm_summary=%ld\n", status);
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per_cpu(ia64_tr_num, cpu) = 8;
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return;
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}
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per_cpu(ia64_tr_num, cpu) = vm_info_1.pal_vm_info_1_s.max_itr_entry+1;
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if (per_cpu(ia64_tr_num, cpu) >
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(vm_info_1.pal_vm_info_1_s.max_dtr_entry+1))
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per_cpu(ia64_tr_num, cpu) =
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vm_info_1.pal_vm_info_1_s.max_dtr_entry+1;
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if (per_cpu(ia64_tr_num, cpu) > IA64_TR_ALLOC_MAX) {
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per_cpu(ia64_tr_num, cpu) = IA64_TR_ALLOC_MAX;
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printk(KERN_DEBUG "TR register number exceeds IA64_TR_ALLOC_MAX!"
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"IA64_TR_ALLOC_MAX should be extended\n");
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}
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}
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/*
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* is_tr_overlap
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*
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* Check overlap with inserted TRs.
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*/
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static int is_tr_overlap(struct ia64_tr_entry *p, u64 va, u64 log_size)
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{
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u64 tr_log_size;
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u64 tr_end;
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u64 va_rr = ia64_get_rr(va);
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u64 va_rid = RR_TO_RID(va_rr);
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u64 va_end = va + (1<<log_size) - 1;
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if (va_rid != RR_TO_RID(p->rr))
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return 0;
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tr_log_size = (p->itir & 0xff) >> 2;
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tr_end = p->ifa + (1<<tr_log_size) - 1;
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if (va > tr_end || p->ifa > va_end)
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return 0;
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return 1;
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}
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/*
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* ia64_insert_tr in virtual mode. Allocate a TR slot
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*
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* target_mask : 0x1 : itr, 0x2 : dtr, 0x3 : idtr
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*
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* va : virtual address.
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* pte : pte entries inserted.
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* log_size: range to be covered.
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*
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* Return value: <0 : error No.
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*
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* >=0 : slot number allocated for TR.
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* Must be called with preemption disabled.
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*/
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int ia64_itr_entry(u64 target_mask, u64 va, u64 pte, u64 log_size)
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{
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int i, r;
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unsigned long psr;
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struct ia64_tr_entry *p;
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int cpu = smp_processor_id();
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r = -EINVAL;
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/*Check overlap with existing TR entries*/
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if (target_mask & 0x1) {
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p = &__per_cpu_idtrs[cpu][0][0];
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for (i = IA64_TR_ALLOC_BASE; i <= per_cpu(ia64_tr_used, cpu);
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i++, p++) {
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if (p->pte & 0x1)
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if (is_tr_overlap(p, va, log_size)) {
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printk(KERN_DEBUG "Overlapped Entry"
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"Inserted for TR Reigster!!\n");
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goto out;
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}
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}
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}
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if (target_mask & 0x2) {
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p = &__per_cpu_idtrs[cpu][1][0];
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for (i = IA64_TR_ALLOC_BASE; i <= per_cpu(ia64_tr_used, cpu);
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i++, p++) {
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if (p->pte & 0x1)
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if (is_tr_overlap(p, va, log_size)) {
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printk(KERN_DEBUG "Overlapped Entry"
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"Inserted for TR Reigster!!\n");
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goto out;
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}
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}
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}
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for (i = IA64_TR_ALLOC_BASE; i < per_cpu(ia64_tr_num, cpu); i++) {
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switch (target_mask & 0x3) {
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case 1:
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if (!(__per_cpu_idtrs[cpu][0][i].pte & 0x1))
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goto found;
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continue;
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case 2:
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if (!(__per_cpu_idtrs[cpu][1][i].pte & 0x1))
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goto found;
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continue;
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case 3:
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if (!(__per_cpu_idtrs[cpu][0][i].pte & 0x1) &&
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!(__per_cpu_idtrs[cpu][1][i].pte & 0x1))
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goto found;
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continue;
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default:
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r = -EINVAL;
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goto out;
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}
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}
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found:
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if (i >= per_cpu(ia64_tr_num, cpu))
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return -EBUSY;
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/*Record tr info for mca hander use!*/
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if (i > per_cpu(ia64_tr_used, cpu))
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per_cpu(ia64_tr_used, cpu) = i;
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psr = ia64_clear_ic();
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if (target_mask & 0x1) {
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ia64_itr(0x1, i, va, pte, log_size);
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ia64_srlz_i();
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p = &__per_cpu_idtrs[cpu][0][i];
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p->ifa = va;
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p->pte = pte;
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p->itir = log_size << 2;
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p->rr = ia64_get_rr(va);
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}
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if (target_mask & 0x2) {
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ia64_itr(0x2, i, va, pte, log_size);
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ia64_srlz_i();
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p = &__per_cpu_idtrs[cpu][1][i];
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p->ifa = va;
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p->pte = pte;
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p->itir = log_size << 2;
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p->rr = ia64_get_rr(va);
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}
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ia64_set_psr(psr);
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r = i;
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out:
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return r;
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}
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EXPORT_SYMBOL_GPL(ia64_itr_entry);
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/*
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* ia64_purge_tr
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*
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* target_mask: 0x1: purge itr, 0x2 : purge dtr, 0x3 purge idtr.
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* slot: slot number to be freed.
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*
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* Must be called with preemption disabled.
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*/
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void ia64_ptr_entry(u64 target_mask, int slot)
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{
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int cpu = smp_processor_id();
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int i;
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struct ia64_tr_entry *p;
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if (slot < IA64_TR_ALLOC_BASE || slot >= per_cpu(ia64_tr_num, cpu))
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return;
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if (target_mask & 0x1) {
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p = &__per_cpu_idtrs[cpu][0][slot];
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if ((p->pte&0x1) && is_tr_overlap(p, p->ifa, p->itir>>2)) {
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p->pte = 0;
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ia64_ptr(0x1, p->ifa, p->itir>>2);
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ia64_srlz_i();
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}
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}
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if (target_mask & 0x2) {
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p = &__per_cpu_idtrs[cpu][1][slot];
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if ((p->pte & 0x1) && is_tr_overlap(p, p->ifa, p->itir>>2)) {
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p->pte = 0;
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ia64_ptr(0x2, p->ifa, p->itir>>2);
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ia64_srlz_i();
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}
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}
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for (i = per_cpu(ia64_tr_used, cpu); i >= IA64_TR_ALLOC_BASE; i--) {
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if ((__per_cpu_idtrs[cpu][0][i].pte & 0x1) ||
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(__per_cpu_idtrs[cpu][1][i].pte & 0x1))
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break;
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}
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per_cpu(ia64_tr_used, cpu) = i;
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}
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EXPORT_SYMBOL_GPL(ia64_ptr_entry);
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@ -31,6 +31,9 @@
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#define IA64_TR_PALCODE 1 /* itr1: maps PALcode as required by EFI */
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#define IA64_TR_CURRENT_STACK 1 /* dtr1: maps kernel's memory- & register-stacks */
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#define IA64_TR_ALLOC_BASE 2 /* itr&dtr: Base of dynamic TR resource*/
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#define IA64_TR_ALLOC_MAX 32 /* Max number for dynamic use*/
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/* Processor status register bits: */
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#define IA64_PSR_BE_BIT 1
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#define IA64_PSR_UP_BIT 2
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@ -64,6 +64,32 @@ struct mmu_gather {
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struct page *pages[FREE_PTE_NR];
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};
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struct ia64_tr_entry {
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u64 ifa;
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u64 itir;
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u64 pte;
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u64 rr;
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}; /*Record for tr entry!*/
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extern int ia64_itr_entry(u64 target_mask, u64 va, u64 pte, u64 log_size);
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extern void ia64_ptr_entry(u64 target_mask, int slot);
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extern struct ia64_tr_entry __per_cpu_idtrs[NR_CPUS][2][IA64_TR_ALLOC_MAX];
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/*
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region register macros
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*/
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#define RR_TO_VE(val) (((val) >> 0) & 0x0000000000000001)
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#define RR_VE(val) (((val) & 0x0000000000000001) << 0)
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#define RR_VE_MASK 0x0000000000000001L
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#define RR_VE_SHIFT 0
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#define RR_TO_PS(val) (((val) >> 2) & 0x000000000000003f)
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#define RR_PS(val) (((val) & 0x000000000000003f) << 2)
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#define RR_PS_MASK 0x00000000000000fcL
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#define RR_PS_SHIFT 2
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#define RR_RID_MASK 0x00000000ffffff00L
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#define RR_TO_RID(val) ((val >> 8) & 0xffffff)
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/* Users of the generic TLB shootdown code must declare this storage space. */
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DECLARE_PER_CPU(struct mmu_gather, mmu_gathers);
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