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i2c: designware: Align defines in i2c-designware-core.h
Align all defines to the same column. Signed-off-by: Jarkko Nikula <jarkko.nikula@linux.intel.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Wolfram Sang <wsa@kernel.org>
This commit is contained in:
Jarkko Nikula
Wolfram Sang
parent
fee61247b7
commit
966b7d3c73
1 changed files with 109 additions and 109 deletions
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@ -18,12 +18,12 @@
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#include <linux/regmap.h>
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#include <linux/types.h>
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#define DW_IC_DEFAULT_FUNCTIONALITY (I2C_FUNC_I2C | \
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I2C_FUNC_SMBUS_BYTE | \
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I2C_FUNC_SMBUS_BYTE_DATA | \
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I2C_FUNC_SMBUS_WORD_DATA | \
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I2C_FUNC_SMBUS_BLOCK_DATA | \
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I2C_FUNC_SMBUS_I2C_BLOCK)
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#define DW_IC_DEFAULT_FUNCTIONALITY (I2C_FUNC_I2C | \
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I2C_FUNC_SMBUS_BYTE | \
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I2C_FUNC_SMBUS_BYTE_DATA | \
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I2C_FUNC_SMBUS_WORD_DATA | \
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I2C_FUNC_SMBUS_BLOCK_DATA | \
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I2C_FUNC_SMBUS_I2C_BLOCK)
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#define DW_IC_CON_MASTER BIT(0)
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#define DW_IC_CON_SPEED_STD (1 << 1)
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@ -43,81 +43,81 @@
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/*
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* Registers offset
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*/
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#define DW_IC_CON 0x00
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#define DW_IC_TAR 0x04
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#define DW_IC_SAR 0x08
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#define DW_IC_DATA_CMD 0x10
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#define DW_IC_SS_SCL_HCNT 0x14
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#define DW_IC_SS_SCL_LCNT 0x18
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#define DW_IC_FS_SCL_HCNT 0x1c
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#define DW_IC_FS_SCL_LCNT 0x20
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#define DW_IC_HS_SCL_HCNT 0x24
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#define DW_IC_HS_SCL_LCNT 0x28
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#define DW_IC_INTR_STAT 0x2c
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#define DW_IC_INTR_MASK 0x30
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#define DW_IC_RAW_INTR_STAT 0x34
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#define DW_IC_RX_TL 0x38
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#define DW_IC_TX_TL 0x3c
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#define DW_IC_CLR_INTR 0x40
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#define DW_IC_CLR_RX_UNDER 0x44
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#define DW_IC_CLR_RX_OVER 0x48
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#define DW_IC_CLR_TX_OVER 0x4c
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#define DW_IC_CLR_RD_REQ 0x50
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#define DW_IC_CLR_TX_ABRT 0x54
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#define DW_IC_CLR_RX_DONE 0x58
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#define DW_IC_CLR_ACTIVITY 0x5c
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#define DW_IC_CLR_STOP_DET 0x60
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#define DW_IC_CLR_START_DET 0x64
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#define DW_IC_CLR_GEN_CALL 0x68
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#define DW_IC_ENABLE 0x6c
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#define DW_IC_STATUS 0x70
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#define DW_IC_TXFLR 0x74
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#define DW_IC_RXFLR 0x78
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#define DW_IC_SDA_HOLD 0x7c
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#define DW_IC_TX_ABRT_SOURCE 0x80
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#define DW_IC_ENABLE_STATUS 0x9c
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#define DW_IC_CLR_RESTART_DET 0xa8
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#define DW_IC_COMP_PARAM_1 0xf4
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#define DW_IC_COMP_VERSION 0xf8
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#define DW_IC_SDA_HOLD_MIN_VERS 0x3131312A
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#define DW_IC_COMP_TYPE 0xfc
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#define DW_IC_COMP_TYPE_VALUE 0x44570140
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#define DW_IC_CON 0x00
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#define DW_IC_TAR 0x04
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#define DW_IC_SAR 0x08
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#define DW_IC_DATA_CMD 0x10
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#define DW_IC_SS_SCL_HCNT 0x14
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#define DW_IC_SS_SCL_LCNT 0x18
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#define DW_IC_FS_SCL_HCNT 0x1c
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#define DW_IC_FS_SCL_LCNT 0x20
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#define DW_IC_HS_SCL_HCNT 0x24
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#define DW_IC_HS_SCL_LCNT 0x28
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#define DW_IC_INTR_STAT 0x2c
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#define DW_IC_INTR_MASK 0x30
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#define DW_IC_RAW_INTR_STAT 0x34
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#define DW_IC_RX_TL 0x38
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#define DW_IC_TX_TL 0x3c
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#define DW_IC_CLR_INTR 0x40
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#define DW_IC_CLR_RX_UNDER 0x44
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#define DW_IC_CLR_RX_OVER 0x48
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#define DW_IC_CLR_TX_OVER 0x4c
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#define DW_IC_CLR_RD_REQ 0x50
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#define DW_IC_CLR_TX_ABRT 0x54
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#define DW_IC_CLR_RX_DONE 0x58
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#define DW_IC_CLR_ACTIVITY 0x5c
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#define DW_IC_CLR_STOP_DET 0x60
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#define DW_IC_CLR_START_DET 0x64
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#define DW_IC_CLR_GEN_CALL 0x68
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#define DW_IC_ENABLE 0x6c
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#define DW_IC_STATUS 0x70
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#define DW_IC_TXFLR 0x74
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#define DW_IC_RXFLR 0x78
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#define DW_IC_SDA_HOLD 0x7c
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#define DW_IC_TX_ABRT_SOURCE 0x80
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#define DW_IC_ENABLE_STATUS 0x9c
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#define DW_IC_CLR_RESTART_DET 0xa8
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#define DW_IC_COMP_PARAM_1 0xf4
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#define DW_IC_COMP_VERSION 0xf8
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#define DW_IC_SDA_HOLD_MIN_VERS 0x3131312A
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#define DW_IC_COMP_TYPE 0xfc
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#define DW_IC_COMP_TYPE_VALUE 0x44570140
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#define DW_IC_INTR_RX_UNDER BIT(0)
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#define DW_IC_INTR_RX_OVER BIT(1)
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#define DW_IC_INTR_RX_FULL BIT(2)
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#define DW_IC_INTR_TX_OVER BIT(3)
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#define DW_IC_INTR_TX_EMPTY BIT(4)
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#define DW_IC_INTR_RD_REQ BIT(5)
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#define DW_IC_INTR_TX_ABRT BIT(6)
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#define DW_IC_INTR_RX_DONE BIT(7)
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#define DW_IC_INTR_ACTIVITY BIT(8)
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#define DW_IC_INTR_STOP_DET BIT(9)
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#define DW_IC_INTR_START_DET BIT(10)
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#define DW_IC_INTR_GEN_CALL BIT(11)
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#define DW_IC_INTR_RESTART_DET BIT(12)
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#define DW_IC_INTR_RX_UNDER BIT(0)
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#define DW_IC_INTR_RX_OVER BIT(1)
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#define DW_IC_INTR_RX_FULL BIT(2)
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#define DW_IC_INTR_TX_OVER BIT(3)
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#define DW_IC_INTR_TX_EMPTY BIT(4)
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#define DW_IC_INTR_RD_REQ BIT(5)
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#define DW_IC_INTR_TX_ABRT BIT(6)
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#define DW_IC_INTR_RX_DONE BIT(7)
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#define DW_IC_INTR_ACTIVITY BIT(8)
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#define DW_IC_INTR_STOP_DET BIT(9)
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#define DW_IC_INTR_START_DET BIT(10)
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#define DW_IC_INTR_GEN_CALL BIT(11)
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#define DW_IC_INTR_RESTART_DET BIT(12)
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#define DW_IC_INTR_DEFAULT_MASK (DW_IC_INTR_RX_FULL | \
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DW_IC_INTR_TX_ABRT | \
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DW_IC_INTR_STOP_DET)
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#define DW_IC_INTR_MASTER_MASK (DW_IC_INTR_DEFAULT_MASK | \
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DW_IC_INTR_TX_EMPTY)
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#define DW_IC_INTR_SLAVE_MASK (DW_IC_INTR_DEFAULT_MASK | \
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DW_IC_INTR_RX_UNDER | \
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DW_IC_INTR_RD_REQ)
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#define DW_IC_INTR_DEFAULT_MASK (DW_IC_INTR_RX_FULL | \
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DW_IC_INTR_TX_ABRT | \
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DW_IC_INTR_STOP_DET)
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#define DW_IC_INTR_MASTER_MASK (DW_IC_INTR_DEFAULT_MASK | \
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DW_IC_INTR_TX_EMPTY)
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#define DW_IC_INTR_SLAVE_MASK (DW_IC_INTR_DEFAULT_MASK | \
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DW_IC_INTR_RX_UNDER | \
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DW_IC_INTR_RD_REQ)
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#define DW_IC_STATUS_ACTIVITY BIT(0)
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#define DW_IC_STATUS_TFE BIT(2)
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#define DW_IC_STATUS_RFNE BIT(3)
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#define DW_IC_STATUS_MASTER_ACTIVITY BIT(5)
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#define DW_IC_STATUS_SLAVE_ACTIVITY BIT(6)
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#define DW_IC_STATUS_ACTIVITY BIT(0)
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#define DW_IC_STATUS_TFE BIT(2)
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#define DW_IC_STATUS_RFNE BIT(3)
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#define DW_IC_STATUS_MASTER_ACTIVITY BIT(5)
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#define DW_IC_STATUS_SLAVE_ACTIVITY BIT(6)
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#define DW_IC_SDA_HOLD_RX_SHIFT 16
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#define DW_IC_SDA_HOLD_RX_MASK GENMASK(23, 16)
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#define DW_IC_SDA_HOLD_RX_SHIFT 16
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#define DW_IC_SDA_HOLD_RX_MASK GENMASK(23, 16)
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#define DW_IC_ERR_TX_ABRT 0x1
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#define DW_IC_ERR_TX_ABRT 0x1
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#define DW_IC_TAR_10BITADDR_MASTER BIT(12)
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#define DW_IC_TAR_10BITADDR_MASTER BIT(12)
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#define DW_IC_COMP_PARAM_1_SPEED_MODE_HIGH (BIT(2) | BIT(3))
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#define DW_IC_COMP_PARAM_1_SPEED_MODE_MASK GENMASK(3, 2)
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@ -125,16 +125,16 @@
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/*
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* Sofware status flags
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*/
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#define STATUS_ACTIVE BIT(0)
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#define STATUS_WRITE_IN_PROGRESS BIT(1)
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#define STATUS_READ_IN_PROGRESS BIT(2)
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#define STATUS_MASK GENMASK(2, 0)
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#define STATUS_ACTIVE BIT(0)
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#define STATUS_WRITE_IN_PROGRESS BIT(1)
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#define STATUS_READ_IN_PROGRESS BIT(2)
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#define STATUS_MASK GENMASK(2, 0)
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/*
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* operation modes
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*/
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#define DW_IC_MASTER 0
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#define DW_IC_SLAVE 1
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#define DW_IC_MASTER 0
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#define DW_IC_SLAVE 1
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/*
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* Hardware abort codes from the DW_IC_TX_ABRT_SOURCE register
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@ -142,20 +142,20 @@
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* Only expected abort codes are listed here
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* refer to the datasheet for the full list
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*/
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#define ABRT_7B_ADDR_NOACK 0
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#define ABRT_10ADDR1_NOACK 1
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#define ABRT_10ADDR2_NOACK 2
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#define ABRT_TXDATA_NOACK 3
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#define ABRT_GCALL_NOACK 4
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#define ABRT_GCALL_READ 5
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#define ABRT_SBYTE_ACKDET 7
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#define ABRT_SBYTE_NORSTRT 9
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#define ABRT_10B_RD_NORSTRT 10
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#define ABRT_MASTER_DIS 11
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#define ARB_LOST 12
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#define ABRT_SLAVE_FLUSH_TXFIFO 13
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#define ABRT_SLAVE_ARBLOST 14
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#define ABRT_SLAVE_RD_INTX 15
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#define ABRT_7B_ADDR_NOACK 0
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#define ABRT_10ADDR1_NOACK 1
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#define ABRT_10ADDR2_NOACK 2
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#define ABRT_TXDATA_NOACK 3
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#define ABRT_GCALL_NOACK 4
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#define ABRT_GCALL_READ 5
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#define ABRT_SBYTE_ACKDET 7
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#define ABRT_SBYTE_NORSTRT 9
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#define ABRT_10B_RD_NORSTRT 10
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#define ABRT_MASTER_DIS 11
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#define ARB_LOST 12
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#define ABRT_SLAVE_FLUSH_TXFIFO 13
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#define ABRT_SLAVE_ARBLOST 14
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#define ABRT_SLAVE_RD_INTX 15
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#define DW_IC_TX_ABRT_7B_ADDR_NOACK BIT(ABRT_7B_ADDR_NOACK)
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#define DW_IC_TX_ABRT_10ADDR1_NOACK BIT(ABRT_10ADDR1_NOACK)
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@ -172,11 +172,11 @@
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#define DW_IC_RX_ABRT_SLAVE_ARBLOST BIT(ABRT_SLAVE_ARBLOST)
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#define DW_IC_RX_ABRT_SLAVE_FLUSH_TXFIFO BIT(ABRT_SLAVE_FLUSH_TXFIFO)
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#define DW_IC_TX_ABRT_NOACK (DW_IC_TX_ABRT_7B_ADDR_NOACK | \
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DW_IC_TX_ABRT_10ADDR1_NOACK | \
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DW_IC_TX_ABRT_10ADDR2_NOACK | \
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DW_IC_TX_ABRT_TXDATA_NOACK | \
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DW_IC_TX_ABRT_GCALL_NOACK)
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#define DW_IC_TX_ABRT_NOACK (DW_IC_TX_ABRT_7B_ADDR_NOACK | \
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DW_IC_TX_ABRT_10ADDR1_NOACK | \
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DW_IC_TX_ABRT_10ADDR2_NOACK | \
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DW_IC_TX_ABRT_TXDATA_NOACK | \
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DW_IC_TX_ABRT_GCALL_NOACK)
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struct clk;
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struct device;
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@ -295,21 +295,21 @@ struct dw_i2c_dev {
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struct i2c_bus_recovery_info rinfo;
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};
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#define ACCESS_INTR_MASK BIT(0)
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#define ACCESS_NO_IRQ_SUSPEND BIT(1)
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#define ARBITRATION_SEMAPHORE BIT(2)
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#define ACCESS_INTR_MASK BIT(0)
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#define ACCESS_NO_IRQ_SUSPEND BIT(1)
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#define ARBITRATION_SEMAPHORE BIT(2)
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#define MODEL_MSCC_OCELOT BIT(8)
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#define MODEL_BAIKAL_BT1 BIT(9)
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#define MODEL_AMD_NAVI_GPU BIT(10)
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#define MODEL_MASK GENMASK(11, 8)
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#define MODEL_MSCC_OCELOT BIT(8)
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#define MODEL_BAIKAL_BT1 BIT(9)
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#define MODEL_AMD_NAVI_GPU BIT(10)
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#define MODEL_MASK GENMASK(11, 8)
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/*
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* Enable UCSI interrupt by writing 0xd at register
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* offset 0x474 specified in hardware specification.
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*/
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#define AMD_UCSI_INTR_REG 0x474
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#define AMD_UCSI_INTR_EN 0xd
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#define AMD_UCSI_INTR_REG 0x474
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#define AMD_UCSI_INTR_EN 0xd
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struct i2c_dw_semaphore_callbacks {
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int (*probe)(struct dw_i2c_dev *dev);
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