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drm/amd/powerplay: Add support functions for CI to ppatomctrl.c
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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2 changed files with 86 additions and 0 deletions
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@ -1418,3 +1418,83 @@ int atomctrl_get_svi2_info(struct pp_hwmgr *hwmgr, uint8_t voltage_type,
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return 0;
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return 0;
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}
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}
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int atomctrl_get_leakage_id_from_efuse(struct pp_hwmgr *hwmgr, uint16_t *virtual_voltage_id)
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{
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int result;
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SET_VOLTAGE_PS_ALLOCATION allocation;
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SET_VOLTAGE_PARAMETERS_V1_3 *voltage_parameters =
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(SET_VOLTAGE_PARAMETERS_V1_3 *)&allocation.sASICSetVoltage;
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voltage_parameters->ucVoltageMode = ATOM_GET_LEAKAGE_ID;
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result = cgs_atom_exec_cmd_table(hwmgr->device,
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GetIndexIntoMasterTable(COMMAND, SetVoltage),
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voltage_parameters);
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*virtual_voltage_id = voltage_parameters->usVoltageLevel;
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return result;
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}
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int atomctrl_get_leakage_vddc_base_on_leakage(struct pp_hwmgr *hwmgr,
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uint16_t *vddc, uint16_t *vddci,
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uint16_t virtual_voltage_id,
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uint16_t efuse_voltage_id)
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{
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int i, j;
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int ix;
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u16 *leakage_bin, *vddc_id_buf, *vddc_buf, *vddci_id_buf, *vddci_buf;
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ATOM_ASIC_PROFILING_INFO_V2_1 *profile;
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*vddc = 0;
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*vddci = 0;
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ix = GetIndexIntoMasterTable(DATA, ASIC_ProfilingInfo);
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profile = (ATOM_ASIC_PROFILING_INFO_V2_1 *)
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cgs_atom_get_data_table(hwmgr->device,
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ix,
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NULL, NULL, NULL);
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if (!profile)
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return -EINVAL;
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if ((profile->asHeader.ucTableFormatRevision >= 2) &&
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(profile->asHeader.ucTableContentRevision >= 1) &&
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(profile->asHeader.usStructureSize >= sizeof(ATOM_ASIC_PROFILING_INFO_V2_1))) {
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leakage_bin = (u16 *)((char *)profile + profile->usLeakageBinArrayOffset);
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vddc_id_buf = (u16 *)((char *)profile + profile->usElbVDDC_IdArrayOffset);
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vddc_buf = (u16 *)((char *)profile + profile->usElbVDDC_LevelArrayOffset);
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if (profile->ucElbVDDC_Num > 0) {
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for (i = 0; i < profile->ucElbVDDC_Num; i++) {
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if (vddc_id_buf[i] == virtual_voltage_id) {
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for (j = 0; j < profile->ucLeakageBinNum; j++) {
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if (efuse_voltage_id <= leakage_bin[j]) {
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*vddc = vddc_buf[j * profile->ucElbVDDC_Num + i];
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break;
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}
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}
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break;
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}
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}
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}
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vddci_id_buf = (u16 *)((char *)profile + profile->usElbVDDCI_IdArrayOffset);
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vddci_buf = (u16 *)((char *)profile + profile->usElbVDDCI_LevelArrayOffset);
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if (profile->ucElbVDDCI_Num > 0) {
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for (i = 0; i < profile->ucElbVDDCI_Num; i++) {
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if (vddci_id_buf[i] == virtual_voltage_id) {
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for (j = 0; j < profile->ucLeakageBinNum; j++) {
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if (efuse_voltage_id <= leakage_bin[j]) {
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*vddci = vddci_buf[j * profile->ucElbVDDC_Num + i];
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break;
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}
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}
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break;
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}
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}
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}
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}
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return 0;
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}
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@ -314,5 +314,11 @@ extern int atomctrl_get_avfs_information(struct pp_hwmgr *hwmgr, struct pp_atom_
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extern int atomctrl_get_svi2_info(struct pp_hwmgr *hwmgr, uint8_t voltage_type,
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extern int atomctrl_get_svi2_info(struct pp_hwmgr *hwmgr, uint8_t voltage_type,
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uint8_t *svd_gpio_id, uint8_t *svc_gpio_id,
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uint8_t *svd_gpio_id, uint8_t *svc_gpio_id,
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uint16_t *load_line);
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uint16_t *load_line);
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extern int atomctrl_get_leakage_vddc_base_on_leakage(struct pp_hwmgr *hwmgr,
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uint16_t *vddc, uint16_t *vddci,
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uint16_t virtual_voltage_id,
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uint16_t efuse_voltage_id);
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extern int atomctrl_get_leakage_id_from_efuse(struct pp_hwmgr *hwmgr, uint16_t *virtual_voltage_id);
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#endif
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#endif
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