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tpm: read burstcount from TPM_STS in one 32-bit transaction
Some chips incorrectly support partial reads from TPM_STS register
at non-zero offsets. Read the entire 32-bits register instead of
making two 8-bit reads to support such devices and reduce the number
of bus transactions when obtaining the burstcount from TPM_STS.
Fixes: 27084efee0
("tpm: driver for next generation TPM chips")
Signed-off-by: Andrey Pronin <apronin@chromium.org>
Reviewed-by: Jarkko Sakkinen <jarkko.sakkinen@linux.intel.com>
Signed-off-by: Jarkko Sakkinen <jarkko.sakkinen@linux.intel.com>
This commit is contained in:
parent
1b0612b040
commit
9754d45e99
1 changed files with 3 additions and 8 deletions
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@ -157,22 +157,17 @@ static int get_burstcount(struct tpm_chip *chip)
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struct tpm_tis_data *priv = dev_get_drvdata(&chip->dev);
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unsigned long stop;
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int burstcnt, rc;
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u8 value;
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u32 value;
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/* wait for burstcount */
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/* which timeout value, spec has 2 answers (c & d) */
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stop = jiffies + chip->timeout_d;
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do {
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rc = tpm_tis_read8(priv, TPM_STS(priv->locality) + 1, &value);
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rc = tpm_tis_read32(priv, TPM_STS(priv->locality), &value);
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if (rc < 0)
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return rc;
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burstcnt = value;
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rc = tpm_tis_read8(priv, TPM_STS(priv->locality) + 2, &value);
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if (rc < 0)
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return rc;
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burstcnt += value << 8;
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burstcnt = (value >> 8) & 0xFFFF;
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if (burstcnt)
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return burstcnt;
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msleep(TPM_TIMEOUT);
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