mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-08-25 02:09:42 +00:00
Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus
Pull MIPS fixes from Ralf Baechle: "Lantiq: - Fix adding xbar resoures causing a panic Loongson3: - Some Loongson 3A don't identify themselves as having an FTLB so hardwire that knowledge into CPU probing. - Handle Loongson 3 TLB peculiarities in the fast path of the RDHWR emulation. - Fix invalid FTLB entries with huge page on VTLB+FTLB platforms - Add missing calculation of S-cache and V-cache cache-way size Ralink: - Fix typos in rt3883 pinctrl data Generic: - Force o32 fp64 support on 32bit MIPS64r6 kernels - Yet another build fix after the linux/sched.h changes - Wire up statx system call - Fix stack unwinding after introduction of IRQ stack - Fix spinlock code to build even for microMIPS with recent binutils SMP-CPS: - Fix retrieval of VPE mask on big endian CPUs" * 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: MIPS: IRQ Stack: Unwind IRQ stack onto task stack MIPS: c-r4k: Fix Loongson-3's vcache/scache waysize calculation MIPS: Flush wrong invalid FTLB entry for huge page MIPS: Check TLB before handle_ri_rdhwr() for Loongson-3 MIPS: Add MIPS_CPU_FTLB for Loongson-3A R2 MIPS: Lantiq: fix missing xbar kernel panic MIPS: smp-cps: Fix retrieval of VPE mask on big endian CPUs MIPS: Wire up statx system call MIPS: Include asm/ptrace.h now linux/sched.h doesn't MIPS: ralink: Fix typos in rt3883 pinctrl MIPS: End spinlocks with .insn MIPS: Force o32 fp64 support on 32bit MIPS64r6 kernels
This commit is contained in:
commit
977674c06b
19 changed files with 122 additions and 46 deletions
|
@ -1531,7 +1531,7 @@ config CPU_MIPS64_R6
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select CPU_SUPPORTS_HIGHMEM
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select CPU_SUPPORTS_MSA
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select GENERIC_CSUM
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select MIPS_O32_FP64_SUPPORT if MIPS32_O32
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select MIPS_O32_FP64_SUPPORT if 32BIT || MIPS32_O32
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select HAVE_KVM
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help
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Choose this option to build a kernel for release 6 or later of the
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@ -21,6 +21,7 @@
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#include <asm/cpu-features.h>
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#include <asm/fpu_emulator.h>
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#include <asm/hazards.h>
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#include <asm/ptrace.h>
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#include <asm/processor.h>
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#include <asm/current.h>
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#include <asm/msa.h>
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@ -18,9 +18,24 @@
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#include <irq.h>
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#define IRQ_STACK_SIZE THREAD_SIZE
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#define IRQ_STACK_START (IRQ_STACK_SIZE - sizeof(unsigned long))
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extern void *irq_stack[NR_CPUS];
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/*
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* The highest address on the IRQ stack contains a dummy frame put down in
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* genex.S (handle_int & except_vec_vi_handler) which is structured as follows:
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*
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* top ------------
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* | task sp | <- irq_stack[cpu] + IRQ_STACK_START
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* ------------
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* | | <- First frame of IRQ context
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* ------------
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*
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* task sp holds a copy of the task stack pointer where the struct pt_regs
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* from exception entry can be found.
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*/
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static inline bool on_irq_stack(int cpu, unsigned long sp)
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{
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unsigned long low = (unsigned long)irq_stack[cpu];
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@ -127,7 +127,7 @@ static inline void arch_spin_lock(arch_spinlock_t *lock)
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" andi %[ticket], %[ticket], 0xffff \n"
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" bne %[ticket], %[my_ticket], 4f \n"
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" subu %[ticket], %[my_ticket], %[ticket] \n"
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"2: \n"
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"2: .insn \n"
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" .subsection 2 \n"
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"4: andi %[ticket], %[ticket], 0xffff \n"
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" sll %[ticket], 5 \n"
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@ -202,7 +202,7 @@ static inline unsigned int arch_spin_trylock(arch_spinlock_t *lock)
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" sc %[ticket], %[ticket_ptr] \n"
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" beqz %[ticket], 1b \n"
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" li %[ticket], 1 \n"
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"2: \n"
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"2: .insn \n"
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" .subsection 2 \n"
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"3: b 2b \n"
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" li %[ticket], 0 \n"
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@ -382,7 +382,7 @@ static inline int arch_read_trylock(arch_rwlock_t *rw)
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" .set reorder \n"
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__WEAK_LLSC_MB
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" li %2, 1 \n"
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"2: \n"
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"2: .insn \n"
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: "=" GCC_OFF_SMALL_ASM() (rw->lock), "=&r" (tmp), "=&r" (ret)
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: GCC_OFF_SMALL_ASM() (rw->lock)
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: "memory");
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@ -422,7 +422,7 @@ static inline int arch_write_trylock(arch_rwlock_t *rw)
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" lui %1, 0x8000 \n"
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" sc %1, %0 \n"
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" li %2, 1 \n"
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"2: \n"
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"2: .insn \n"
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: "=" GCC_OFF_SMALL_ASM() (rw->lock), "=&r" (tmp),
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"=&r" (ret)
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: GCC_OFF_SMALL_ASM() (rw->lock)
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|
|
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@ -386,17 +386,18 @@
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#define __NR_pkey_mprotect (__NR_Linux + 363)
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#define __NR_pkey_alloc (__NR_Linux + 364)
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#define __NR_pkey_free (__NR_Linux + 365)
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#define __NR_statx (__NR_Linux + 366)
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/*
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* Offset of the last Linux o32 flavoured syscall
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*/
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#define __NR_Linux_syscalls 365
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#define __NR_Linux_syscalls 366
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#endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */
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#define __NR_O32_Linux 4000
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#define __NR_O32_Linux_syscalls 365
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#define __NR_O32_Linux_syscalls 366
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#if _MIPS_SIM == _MIPS_SIM_ABI64
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@ -730,16 +731,17 @@
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#define __NR_pkey_mprotect (__NR_Linux + 323)
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#define __NR_pkey_alloc (__NR_Linux + 324)
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#define __NR_pkey_free (__NR_Linux + 325)
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#define __NR_statx (__NR_Linux + 326)
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/*
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* Offset of the last Linux 64-bit flavoured syscall
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*/
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#define __NR_Linux_syscalls 325
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#define __NR_Linux_syscalls 326
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#endif /* _MIPS_SIM == _MIPS_SIM_ABI64 */
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#define __NR_64_Linux 5000
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#define __NR_64_Linux_syscalls 325
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#define __NR_64_Linux_syscalls 326
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#if _MIPS_SIM == _MIPS_SIM_NABI32
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@ -1077,15 +1079,16 @@
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#define __NR_pkey_mprotect (__NR_Linux + 327)
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#define __NR_pkey_alloc (__NR_Linux + 328)
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#define __NR_pkey_free (__NR_Linux + 329)
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#define __NR_statx (__NR_Linux + 330)
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/*
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* Offset of the last N32 flavoured syscall
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*/
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#define __NR_Linux_syscalls 329
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#define __NR_Linux_syscalls 330
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#endif /* _MIPS_SIM == _MIPS_SIM_NABI32 */
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#define __NR_N32_Linux 6000
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#define __NR_N32_Linux_syscalls 329
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#define __NR_N32_Linux_syscalls 330
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#endif /* _UAPI_ASM_UNISTD_H */
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@ -102,6 +102,7 @@ void output_thread_info_defines(void)
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DEFINE(_THREAD_SIZE, THREAD_SIZE);
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DEFINE(_THREAD_MASK, THREAD_MASK);
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DEFINE(_IRQ_STACK_SIZE, IRQ_STACK_SIZE);
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DEFINE(_IRQ_STACK_START, IRQ_STACK_START);
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BLANK();
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}
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@ -361,7 +361,7 @@ LEAF(mips_cps_get_bootcfg)
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END(mips_cps_get_bootcfg)
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LEAF(mips_cps_boot_vpes)
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PTR_L ta2, COREBOOTCFG_VPEMASK(a0)
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lw ta2, COREBOOTCFG_VPEMASK(a0)
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PTR_L ta3, COREBOOTCFG_VPECONFIG(a0)
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#if defined(CONFIG_CPU_MIPSR6)
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@ -1824,7 +1824,7 @@ static inline void cpu_probe_loongson(struct cpuinfo_mips *c, unsigned int cpu)
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}
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decode_configs(c);
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c->options |= MIPS_CPU_TLBINV | MIPS_CPU_LDPTE;
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c->options |= MIPS_CPU_FTLB | MIPS_CPU_TLBINV | MIPS_CPU_LDPTE;
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c->writecombine = _CACHE_UNCACHED_ACCELERATED;
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break;
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default:
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@ -215,9 +215,11 @@ NESTED(handle_int, PT_SIZE, sp)
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beq t0, t1, 2f
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/* Switch to IRQ stack */
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li t1, _IRQ_STACK_SIZE
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li t1, _IRQ_STACK_START
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PTR_ADD sp, t0, t1
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/* Save task's sp on IRQ stack so that unwinding can follow it */
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LONG_S s1, 0(sp)
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2:
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jal plat_irq_dispatch
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@ -325,9 +327,11 @@ NESTED(except_vec_vi_handler, 0, sp)
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beq t0, t1, 2f
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/* Switch to IRQ stack */
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li t1, _IRQ_STACK_SIZE
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li t1, _IRQ_STACK_START
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PTR_ADD sp, t0, t1
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/* Save task's sp on IRQ stack so that unwinding can follow it */
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LONG_S s1, 0(sp)
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2:
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jalr v0
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@ -519,7 +523,7 @@ NESTED(nmi_handler, PT_SIZE, sp)
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BUILD_HANDLER reserved reserved sti verbose /* others */
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.align 5
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LEAF(handle_ri_rdhwr_vivt)
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LEAF(handle_ri_rdhwr_tlbp)
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.set push
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.set noat
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.set noreorder
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@ -538,7 +542,7 @@ NESTED(nmi_handler, PT_SIZE, sp)
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.set pop
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bltz k1, handle_ri /* slow path */
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/* fall thru */
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END(handle_ri_rdhwr_vivt)
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END(handle_ri_rdhwr_tlbp)
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LEAF(handle_ri_rdhwr)
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.set push
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@ -488,31 +488,52 @@ unsigned long notrace unwind_stack_by_address(unsigned long stack_page,
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unsigned long pc,
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unsigned long *ra)
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{
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unsigned long low, high, irq_stack_high;
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struct mips_frame_info info;
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unsigned long size, ofs;
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struct pt_regs *regs;
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int leaf;
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extern void ret_from_irq(void);
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extern void ret_from_exception(void);
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if (!stack_page)
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return 0;
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/*
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* If we reached the bottom of interrupt context,
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* return saved pc in pt_regs.
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* IRQ stacks start at IRQ_STACK_START
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* task stacks at THREAD_SIZE - 32
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*/
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if (pc == (unsigned long)ret_from_irq ||
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pc == (unsigned long)ret_from_exception) {
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struct pt_regs *regs;
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if (*sp >= stack_page &&
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*sp + sizeof(*regs) <= stack_page + THREAD_SIZE - 32) {
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regs = (struct pt_regs *)*sp;
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pc = regs->cp0_epc;
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if (!user_mode(regs) && __kernel_text_address(pc)) {
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*sp = regs->regs[29];
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*ra = regs->regs[31];
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return pc;
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}
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low = stack_page;
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if (!preemptible() && on_irq_stack(raw_smp_processor_id(), *sp)) {
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high = stack_page + IRQ_STACK_START;
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irq_stack_high = high;
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} else {
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high = stack_page + THREAD_SIZE - 32;
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irq_stack_high = 0;
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}
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/*
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* If we reached the top of the interrupt stack, start unwinding
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* the interrupted task stack.
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*/
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if (unlikely(*sp == irq_stack_high)) {
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unsigned long task_sp = *(unsigned long *)*sp;
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/*
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* Check that the pointer saved in the IRQ stack head points to
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* something within the stack of the current task
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*/
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if (!object_is_on_stack((void *)task_sp))
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return 0;
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/*
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* Follow pointer to tasks kernel stack frame where interrupted
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* state was saved.
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*/
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regs = (struct pt_regs *)task_sp;
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pc = regs->cp0_epc;
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if (!user_mode(regs) && __kernel_text_address(pc)) {
|
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*sp = regs->regs[29];
|
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*ra = regs->regs[31];
|
||||
return pc;
|
||||
}
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||||
return 0;
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||||
}
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||||
|
@ -533,8 +554,7 @@ unsigned long notrace unwind_stack_by_address(unsigned long stack_page,
|
|||
if (leaf < 0)
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return 0;
|
||||
|
||||
if (*sp < stack_page ||
|
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*sp + info.frame_size > stack_page + THREAD_SIZE - 32)
|
||||
if (*sp < low || *sp + info.frame_size > high)
|
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return 0;
|
||||
|
||||
if (leaf)
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||||
|
|
|
@ -600,3 +600,4 @@ EXPORT(sys_call_table)
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PTR sys_pkey_mprotect
|
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PTR sys_pkey_alloc
|
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PTR sys_pkey_free /* 4365 */
|
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PTR sys_statx
|
||||
|
|
|
@ -438,4 +438,5 @@ EXPORT(sys_call_table)
|
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PTR sys_pkey_mprotect
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PTR sys_pkey_alloc
|
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PTR sys_pkey_free /* 5325 */
|
||||
PTR sys_statx
|
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.size sys_call_table,.-sys_call_table
|
||||
|
|
|
@ -433,4 +433,5 @@ EXPORT(sysn32_call_table)
|
|||
PTR sys_pkey_mprotect
|
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PTR sys_pkey_alloc
|
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PTR sys_pkey_free
|
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PTR sys_statx /* 6330 */
|
||||
.size sysn32_call_table,.-sysn32_call_table
|
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|
|
|
@ -588,4 +588,5 @@ EXPORT(sys32_call_table)
|
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PTR sys_pkey_mprotect
|
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PTR sys_pkey_alloc
|
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PTR sys_pkey_free /* 4365 */
|
||||
PTR sys_statx
|
||||
.size sys32_call_table,.-sys32_call_table
|
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|
|
|
@ -83,7 +83,7 @@ extern asmlinkage void handle_dbe(void);
|
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extern asmlinkage void handle_sys(void);
|
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extern asmlinkage void handle_bp(void);
|
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extern asmlinkage void handle_ri(void);
|
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extern asmlinkage void handle_ri_rdhwr_vivt(void);
|
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extern asmlinkage void handle_ri_rdhwr_tlbp(void);
|
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extern asmlinkage void handle_ri_rdhwr(void);
|
||||
extern asmlinkage void handle_cpu(void);
|
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extern asmlinkage void handle_ov(void);
|
||||
|
@ -2408,9 +2408,18 @@ void __init trap_init(void)
|
|||
|
||||
set_except_vector(EXCCODE_SYS, handle_sys);
|
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set_except_vector(EXCCODE_BP, handle_bp);
|
||||
set_except_vector(EXCCODE_RI, rdhwr_noopt ? handle_ri :
|
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(cpu_has_vtag_icache ?
|
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handle_ri_rdhwr_vivt : handle_ri_rdhwr));
|
||||
|
||||
if (rdhwr_noopt)
|
||||
set_except_vector(EXCCODE_RI, handle_ri);
|
||||
else {
|
||||
if (cpu_has_vtag_icache)
|
||||
set_except_vector(EXCCODE_RI, handle_ri_rdhwr_tlbp);
|
||||
else if (current_cpu_type() == CPU_LOONGSON3)
|
||||
set_except_vector(EXCCODE_RI, handle_ri_rdhwr_tlbp);
|
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else
|
||||
set_except_vector(EXCCODE_RI, handle_ri_rdhwr);
|
||||
}
|
||||
|
||||
set_except_vector(EXCCODE_CPU, handle_cpu);
|
||||
set_except_vector(EXCCODE_OV, handle_ov);
|
||||
set_except_vector(EXCCODE_TR, handle_tr);
|
||||
|
|
|
@ -467,7 +467,7 @@ void __init ltq_soc_init(void)
|
|||
|
||||
if (!np_xbar)
|
||||
panic("Failed to load xbar nodes from devicetree");
|
||||
if (of_address_to_resource(np_pmu, 0, &res_xbar))
|
||||
if (of_address_to_resource(np_xbar, 0, &res_xbar))
|
||||
panic("Failed to get xbar resources");
|
||||
if (!request_mem_region(res_xbar.start, resource_size(&res_xbar),
|
||||
res_xbar.name))
|
||||
|
|
|
@ -1562,6 +1562,7 @@ static void probe_vcache(void)
|
|||
vcache_size = c->vcache.sets * c->vcache.ways * c->vcache.linesz;
|
||||
|
||||
c->vcache.waybit = 0;
|
||||
c->vcache.waysize = vcache_size / c->vcache.ways;
|
||||
|
||||
pr_info("Unified victim cache %ldkB %s, linesize %d bytes.\n",
|
||||
vcache_size >> 10, way_string[c->vcache.ways], c->vcache.linesz);
|
||||
|
@ -1664,6 +1665,7 @@ static void __init loongson3_sc_init(void)
|
|||
/* Loongson-3 has 4 cores, 1MB scache for each. scaches are shared */
|
||||
scache_size *= 4;
|
||||
c->scache.waybit = 0;
|
||||
c->scache.waysize = scache_size / c->scache.ways;
|
||||
pr_info("Unified secondary cache %ldkB %s, linesize %d bytes.\n",
|
||||
scache_size >> 10, way_string[c->scache.ways], c->scache.linesz);
|
||||
if (scache_size)
|
||||
|
|
|
@ -760,7 +760,8 @@ static void build_huge_update_entries(u32 **p, unsigned int pte,
|
|||
static void build_huge_handler_tail(u32 **p, struct uasm_reloc **r,
|
||||
struct uasm_label **l,
|
||||
unsigned int pte,
|
||||
unsigned int ptr)
|
||||
unsigned int ptr,
|
||||
unsigned int flush)
|
||||
{
|
||||
#ifdef CONFIG_SMP
|
||||
UASM_i_SC(p, pte, 0, ptr);
|
||||
|
@ -769,6 +770,22 @@ static void build_huge_handler_tail(u32 **p, struct uasm_reloc **r,
|
|||
#else
|
||||
UASM_i_SW(p, pte, 0, ptr);
|
||||
#endif
|
||||
if (cpu_has_ftlb && flush) {
|
||||
BUG_ON(!cpu_has_tlbinv);
|
||||
|
||||
UASM_i_MFC0(p, ptr, C0_ENTRYHI);
|
||||
uasm_i_ori(p, ptr, ptr, MIPS_ENTRYHI_EHINV);
|
||||
UASM_i_MTC0(p, ptr, C0_ENTRYHI);
|
||||
build_tlb_write_entry(p, l, r, tlb_indexed);
|
||||
|
||||
uasm_i_xori(p, ptr, ptr, MIPS_ENTRYHI_EHINV);
|
||||
UASM_i_MTC0(p, ptr, C0_ENTRYHI);
|
||||
build_huge_update_entries(p, pte, ptr);
|
||||
build_huge_tlb_write_entry(p, l, r, pte, tlb_random, 0);
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
build_huge_update_entries(p, pte, ptr);
|
||||
build_huge_tlb_write_entry(p, l, r, pte, tlb_indexed, 0);
|
||||
}
|
||||
|
@ -2199,7 +2216,7 @@ static void build_r4000_tlb_load_handler(void)
|
|||
uasm_l_tlbl_goaround2(&l, p);
|
||||
}
|
||||
uasm_i_ori(&p, wr.r1, wr.r1, (_PAGE_ACCESSED | _PAGE_VALID));
|
||||
build_huge_handler_tail(&p, &r, &l, wr.r1, wr.r2);
|
||||
build_huge_handler_tail(&p, &r, &l, wr.r1, wr.r2, 1);
|
||||
#endif
|
||||
|
||||
uasm_l_nopage_tlbl(&l, p);
|
||||
|
@ -2254,7 +2271,7 @@ static void build_r4000_tlb_store_handler(void)
|
|||
build_tlb_probe_entry(&p);
|
||||
uasm_i_ori(&p, wr.r1, wr.r1,
|
||||
_PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID | _PAGE_DIRTY);
|
||||
build_huge_handler_tail(&p, &r, &l, wr.r1, wr.r2);
|
||||
build_huge_handler_tail(&p, &r, &l, wr.r1, wr.r2, 1);
|
||||
#endif
|
||||
|
||||
uasm_l_nopage_tlbs(&l, p);
|
||||
|
@ -2310,7 +2327,7 @@ static void build_r4000_tlb_modify_handler(void)
|
|||
build_tlb_probe_entry(&p);
|
||||
uasm_i_ori(&p, wr.r1, wr.r1,
|
||||
_PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID | _PAGE_DIRTY);
|
||||
build_huge_handler_tail(&p, &r, &l, wr.r1, wr.r2);
|
||||
build_huge_handler_tail(&p, &r, &l, wr.r1, wr.r2, 0);
|
||||
#endif
|
||||
|
||||
uasm_l_nopage_tlbm(&l, p);
|
||||
|
|
|
@ -35,7 +35,7 @@ static struct rt2880_pmx_func uartlite_func[] = { FUNC("uartlite", 0, 15, 2) };
|
|||
static struct rt2880_pmx_func jtag_func[] = { FUNC("jtag", 0, 17, 5) };
|
||||
static struct rt2880_pmx_func mdio_func[] = { FUNC("mdio", 0, 22, 2) };
|
||||
static struct rt2880_pmx_func lna_a_func[] = { FUNC("lna a", 0, 32, 3) };
|
||||
static struct rt2880_pmx_func lna_g_func[] = { FUNC("lna a", 0, 35, 3) };
|
||||
static struct rt2880_pmx_func lna_g_func[] = { FUNC("lna g", 0, 35, 3) };
|
||||
static struct rt2880_pmx_func pci_func[] = {
|
||||
FUNC("pci-dev", 0, 40, 32),
|
||||
FUNC("pci-host2", 1, 40, 32),
|
||||
|
@ -43,7 +43,7 @@ static struct rt2880_pmx_func pci_func[] = {
|
|||
FUNC("pci-fnc", 3, 40, 32)
|
||||
};
|
||||
static struct rt2880_pmx_func ge1_func[] = { FUNC("ge1", 0, 72, 12) };
|
||||
static struct rt2880_pmx_func ge2_func[] = { FUNC("ge1", 0, 84, 12) };
|
||||
static struct rt2880_pmx_func ge2_func[] = { FUNC("ge2", 0, 84, 12) };
|
||||
|
||||
static struct rt2880_pmx_group rt3883_pinmux_data[] = {
|
||||
GRP("i2c", i2c_func, 1, RT3883_GPIO_MODE_I2C),
|
||||
|
|
Loading…
Reference in a new issue