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powerpc: Register defines for various transactional memory registers
Defines for MSR bits and transactional memory related SPRs TFIAR, TEXASR and TEXASRU. Signed-off-by: Matt Evans <matt@ozlabs.org> Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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@ -29,6 +29,10 @@
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#define MSR_SF_LG 63 /* Enable 64 bit mode */
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#define MSR_ISF_LG 61 /* Interrupt 64b mode valid on 630 */
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#define MSR_HV_LG 60 /* Hypervisor state */
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#define MSR_TS_T_LG 34 /* Trans Mem state: Transactional */
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#define MSR_TS_S_LG 33 /* Trans Mem state: Suspended */
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#define MSR_TS_LG 33 /* Trans Mem state (2 bits) */
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#define MSR_TM_LG 32 /* Trans Mem Available */
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#define MSR_VEC_LG 25 /* Enable AltiVec */
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#define MSR_VSX_LG 23 /* Enable VSX */
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#define MSR_POW_LG 18 /* Enable Power Management */
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@ -98,6 +102,25 @@
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#define MSR_RI __MASK(MSR_RI_LG) /* Recoverable Exception */
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#define MSR_LE __MASK(MSR_LE_LG) /* Little Endian */
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#define MSR_TM __MASK(MSR_TM_LG) /* Transactional Mem Available */
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#define MSR_TS_N 0 /* Non-transactional */
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#define MSR_TS_S __MASK(MSR_TS_S_LG) /* Transaction Suspended */
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#define MSR_TS_T __MASK(MSR_TS_T_LG) /* Transaction Transactional */
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#define MSR_TS_MASK (MSR_TS_T | MSR_TS_S) /* Transaction State bits */
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#define MSR_TM_ACTIVE(x) (((x) & MSR_TS_MASK) != 0) /* Transaction active? */
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#define MSR_TM_TRANSACTIONAL(x) (((x) & MSR_TS_MASK) == MSR_TS_T)
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#define MSR_TM_SUSPENDED(x) (((x) & MSR_TS_MASK) == MSR_TS_S)
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/* Reason codes describing kernel causes for transaction aborts. By
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convention, bit0 is copied to TEXASR[56] (IBM bit 7) which is set if
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the failure is persistent.
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*/
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#define TM_CAUSE_RESCHED 0xfe
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#define TM_CAUSE_TLBI 0xfc
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#define TM_CAUSE_FAC_UNAV 0xfa
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#define TM_CAUSE_SYSCALL 0xf9 /* Persistent */
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#define TM_CAUSE_MISC 0xf6
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#if defined(CONFIG_PPC_BOOK3S_64)
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#define MSR_64BIT MSR_SF
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@ -193,6 +216,10 @@
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#define SPRN_UAMOR 0x9d /* User Authority Mask Override Register */
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#define SPRN_AMOR 0x15d /* Authority Mask Override Register */
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#define SPRN_ACOP 0x1F /* Available Coprocessor Register */
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#define SPRN_TFIAR 0x81 /* Transaction Failure Inst Addr */
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#define SPRN_TEXASR 0x82 /* Transaction EXception & Summary */
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#define SPRN_TEXASRU 0x83 /* '' '' '' Upper 32 */
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#define SPRN_TFHAR 0x80 /* Transaction Failure Handler Addr */
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#define SPRN_CTRLF 0x088
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#define SPRN_CTRLT 0x098
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#define CTRL_CT 0xc0000000 /* current thread */
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