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mlxsw: reg: Add MTUTC register's fields for supporting PTP in Spectrum-2
The MTUTC register configures the HW UTC counter. Add the relevant fields and operations to support PTP in Spectrum-2 and update mlxsw_reg_mtutc_pack() with the new fields for a future use. Signed-off-by: Danielle Ratson <danieller@nvidia.com> Signed-off-by: Amit Cohen <amcohen@nvidia.com> Reviewed-by: Petr Machata <petrm@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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2 changed files with 31 additions and 4 deletions
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@ -10347,6 +10347,8 @@ MLXSW_REG_DEFINE(mtutc, MLXSW_REG_MTUTC_ID, MLXSW_REG_MTUTC_LEN);
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enum mlxsw_reg_mtutc_operation {
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MLXSW_REG_MTUTC_OPERATION_SET_TIME_AT_NEXT_SEC = 0,
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MLXSW_REG_MTUTC_OPERATION_SET_TIME_IMMEDIATE = 1,
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MLXSW_REG_MTUTC_OPERATION_ADJUST_TIME = 2,
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MLXSW_REG_MTUTC_OPERATION_ADJUST_FREQ = 3,
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};
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@ -10359,25 +10361,50 @@ MLXSW_ITEM32(reg, mtutc, operation, 0x00, 0, 4);
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/* reg_mtutc_freq_adjustment
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* Frequency adjustment: Every PPS the HW frequency will be
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* adjusted by this value. Units of HW clock, where HW counts
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* 10^9 HW clocks for 1 HW second.
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* 10^9 HW clocks for 1 HW second. Range is from -50,000,000 to +50,000,000.
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* In Spectrum-2, the field is reversed, positive values mean to decrease the
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* frequency.
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* Access: RW
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*/
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MLXSW_ITEM32(reg, mtutc, freq_adjustment, 0x04, 0, 32);
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#define MLXSW_REG_MTUTC_MAX_FREQ_ADJ (50 * 1000 * 1000)
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/* reg_mtutc_utc_sec
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* UTC seconds.
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* Access: WO
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*/
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MLXSW_ITEM32(reg, mtutc, utc_sec, 0x10, 0, 32);
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/* reg_mtutc_utc_nsec
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* UTC nSecs.
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* Range 0..(10^9-1)
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* Updated when operation is SET_TIME_IMMEDIATE.
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* Reserved on Spectrum-1.
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* Access: WO
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*/
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MLXSW_ITEM32(reg, mtutc, utc_nsec, 0x14, 0, 30);
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/* reg_mtutc_time_adjustment
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* Time adjustment.
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* Units of nSec.
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* Range is from -32768 to +32767.
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* Updated when operation is ADJUST_TIME.
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* Reserved on Spectrum-1.
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* Access: WO
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*/
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MLXSW_ITEM32(reg, mtutc, time_adjustment, 0x18, 0, 32);
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static inline void
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mlxsw_reg_mtutc_pack(char *payload, enum mlxsw_reg_mtutc_operation oper,
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u32 freq_adj, u32 utc_sec)
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u32 freq_adj, u32 utc_sec, u32 utc_nsec, u32 time_adj)
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{
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MLXSW_REG_ZERO(mtutc, payload);
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mlxsw_reg_mtutc_operation_set(payload, oper);
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mlxsw_reg_mtutc_freq_adjustment_set(payload, freq_adj);
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mlxsw_reg_mtutc_utc_sec_set(payload, utc_sec);
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mlxsw_reg_mtutc_utc_nsec_set(payload, utc_nsec);
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mlxsw_reg_mtutc_time_adjustment_set(payload, time_adj);
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}
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/* MCQI - Management Component Query Information
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@ -107,7 +107,7 @@ mlxsw_sp1_ptp_phc_adjfreq(struct mlxsw_sp_ptp_clock *clock, int freq_adj)
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char mtutc_pl[MLXSW_REG_MTUTC_LEN];
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mlxsw_reg_mtutc_pack(mtutc_pl, MLXSW_REG_MTUTC_OPERATION_ADJUST_FREQ,
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freq_adj, 0);
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freq_adj, 0, 0, 0);
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return mlxsw_reg_write(mlxsw_core, MLXSW_REG(mtutc), mtutc_pl);
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}
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@ -144,7 +144,7 @@ mlxsw_sp1_ptp_phc_settime(struct mlxsw_sp_ptp_clock *clock, u64 nsec)
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mlxsw_reg_mtutc_pack(mtutc_pl,
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MLXSW_REG_MTUTC_OPERATION_SET_TIME_AT_NEXT_SEC,
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0, next_sec);
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0, next_sec, 0, 0);
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return mlxsw_reg_write(mlxsw_core, MLXSW_REG(mtutc), mtutc_pl);
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}
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