ARM: dts: imx6qdl-sabreauto: Add audio support
Add ESAI, ASRC, CS42888 for imx6qdl-sabreauto board Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
This commit is contained in:
Shengjiu Wang
Shawn Guo
parent
2d4e4a62f4
commit
97dae8590f
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@ -28,6 +28,51 @@
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};
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};
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clocks {
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codec_osc: anaclk2 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <24576000>;
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};
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};
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regulators {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <0>;
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reg_audio: regulator@0 {
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compatible = "regulator-fixed";
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reg = <0>;
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regulator-name = "cs42888_supply";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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};
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sound-cs42888 {
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compatible = "fsl,imx6-sabreauto-cs42888",
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"fsl,imx-audio-cs42888";
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model = "imx-cs42888";
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audio-cpu = <&esai>;
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audio-asrc = <&asrc>;
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audio-codec = <&codec>;
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audio-routing =
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"Line Out Jack", "AOUT1L",
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"Line Out Jack", "AOUT1R",
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"Line Out Jack", "AOUT2L",
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"Line Out Jack", "AOUT2R",
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"Line Out Jack", "AOUT3L",
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"Line Out Jack", "AOUT3R",
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"Line Out Jack", "AOUT4L",
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"Line Out Jack", "AOUT4R",
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"AIN1L", "Line In Jack",
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"AIN1R", "Line In Jack",
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"AIN2L", "Line In Jack",
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"AIN2R", "Line In Jack";
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};
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sound-spdif {
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compatible = "fsl,imx-audio-spdif",
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"fsl,imx-sabreauto-spdif";
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@ -45,6 +90,15 @@
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};
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};
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&clks {
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assigned-clocks = <&clks IMX6QDL_PLL4_BYPASS_SRC>,
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<&clks IMX6QDL_PLL4_BYPASS>,
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<&clks IMX6QDL_CLK_PLL4_POST_DIV>;
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assigned-clock-parents = <&clks IMX6QDL_CLK_LVDS2_IN>,
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<&clks IMX6QDL_PLL4_BYPASS_SRC>;
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assigned-clock-rates = <0>, <0>, <24576000>;
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};
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&ecspi1 {
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fsl,spi-num-chipselects = <1>;
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cs-gpios = <&gpio3 19 0>;
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@ -61,6 +115,16 @@
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};
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};
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&esai {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_esai>;
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assigned-clocks = <&clks IMX6QDL_CLK_ESAI_SEL>,
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<&clks IMX6QDL_CLK_ESAI_EXTAL>;
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assigned-clock-parents = <&clks IMX6QDL_CLK_PLL4_AUDIO_DIV>;
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assigned-clock-rates = <0>, <24576000>;
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status = "okay";
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};
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&fec {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_enet>;
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@ -184,6 +248,18 @@
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};
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};
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};
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codec: cs42888@48 {
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compatible = "cirrus,cs42888";
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reg = <0x48>;
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clocks = <&codec_osc>;
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clock-names = "mclk";
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VA-supply = <®_audio>;
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VD-supply = <®_audio>;
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VLS-supply = <®_audio>;
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VLC-supply = <®_audio>;
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};
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};
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&i2c3 {
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@ -261,6 +337,21 @@
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>;
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};
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pinctrl_esai: esaigrp {
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fsl,pins = <
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MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1b030
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MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS 0x1b030
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MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x1b030
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MX6QDL_PAD_GPIO_5__ESAI_TX2_RX3 0x1b030
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MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1 0x1b030
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MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0 0x1b030
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MX6QDL_PAD_GPIO_17__ESAI_TX0 0x1b030
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MX6QDL_PAD_NANDF_CS3__ESAI_TX1 0x1b030
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MX6QDL_PAD_ENET_MDIO__ESAI_RX_CLK 0x1b030
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MX6QDL_PAD_GPIO_9__ESAI_RX_FS 0x1b030
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>;
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};
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pinctrl_gpio_leds: gpioledsgrp {
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fsl,pins = <
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MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x80000000
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@ -300,8 +300,19 @@
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};
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esai: esai@02024000 {
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#sound-dai-cells = <0>;
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compatible = "fsl,imx35-esai";
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reg = <0x02024000 0x4000>;
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interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks IMX6QDL_CLK_ESAI_IPG>,
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<&clks IMX6QDL_CLK_ESAI_MEM>,
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<&clks IMX6QDL_CLK_ESAI_EXTAL>,
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<&clks IMX6QDL_CLK_ESAI_IPG>,
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<&clks IMX6QDL_CLK_SPBA>;
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clock-names = "core", "mem", "extal", "fsys", "dma";
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dmas = <&sdma 23 21 0>, <&sdma 24 21 0>;
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dma-names = "rx", "tx";
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status = "disabled";
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};
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ssi1: ssi@02028000 {
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@ -353,8 +364,28 @@
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};
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asrc: asrc@02034000 {
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compatible = "fsl,imx53-asrc";
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reg = <0x02034000 0x4000>;
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interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks IMX6QDL_CLK_ASRC_IPG>,
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<&clks IMX6QDL_CLK_ASRC_MEM>, <&clks 0>,
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<&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
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<&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
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<&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
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<&clks IMX6QDL_CLK_ASRC>, <&clks 0>, <&clks 0>,
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<&clks IMX6QDL_CLK_SPBA>;
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clock-names = "mem", "ipg", "asrck_0",
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"asrck_1", "asrck_2", "asrck_3", "asrck_4",
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"asrck_5", "asrck_6", "asrck_7", "asrck_8",
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"asrck_9", "asrck_a", "asrck_b", "asrck_c",
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"asrck_d", "asrck_e", "asrck_f", "dma";
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dmas = <&sdma 17 23 1>, <&sdma 18 23 1>, <&sdma 19 23 1>,
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<&sdma 20 23 1>, <&sdma 21 23 1>, <&sdma 22 23 1>;
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dma-names = "rxa", "rxb", "rxc",
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"txa", "txb", "txc";
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fsl,asrc-rate = <48000>;
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fsl,asrc-width = <16>;
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status = "okay";
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};
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spba@0203c000 {
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