clocksource/drivers/timer-riscv: Clear timer interrupt on timer initialization
[ Upstream commit8248ca30ef
] In the RISC-V specification, the stimecmp register doesn't have a default value. To prevent the timer interrupt from being triggered during timer initialization, clear the timer interrupt by writing stimecmp with a maximum value. Fixes:9f7a8ff639
("RISC-V: Prefer sstc extension if available") Cc: <stable@vger.kernel.org> Signed-off-by: Ley Foon Tan <leyfoon.tan@starfivetech.com> Reviewed-by: Samuel Holland <samuel.holland@sifive.com> Tested-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Atish Patra <atishp@rivosinc.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Link: https://lore.kernel.org/r/20240306172330.255844-1-leyfoon.tan@starfivetech.com Signed-off-by: Sasha Levin <sashal@kernel.org>
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@ -108,6 +108,9 @@ static int riscv_timer_starting_cpu(unsigned int cpu)
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{
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struct clock_event_device *ce = per_cpu_ptr(&riscv_clock_event, cpu);
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/* Clear timer interrupt */
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riscv_clock_event_stop();
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ce->cpumask = cpumask_of(cpu);
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ce->irq = riscv_clock_event_irq;
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if (riscv_timer_cannot_wake_cpu)
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