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ARM: 6794/1: SPEAr: Append UL to device address macros.
Reviewed-by: Stanley Miao <stanley.miao@windriver.com> Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com> Signed-off-by: Rajeev Kumar <rajeev-dlh.kumar@st.com> Signed-off-by: Viresh Kumar <viresh.kumar@st.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Shiraz Hashim
Russell King
parent
8fc4ef451e
commit
981a95d371
5 changed files with 126 additions and 123 deletions
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@ -14,60 +14,61 @@
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#ifndef __MACH_SPEAR3XX_H
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#define __MACH_SPEAR3XX_H
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#include <asm/memory.h>
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#include <mach/spear300.h>
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#include <mach/spear310.h>
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#include <mach/spear320.h>
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#define SPEAR3XX_ML_SDRAM_BASE 0x00000000
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#define SPEAR3XX_ML_SDRAM_BASE UL(0x00000000)
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#define SPEAR3XX_ICM9_BASE 0xC0000000
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#define SPEAR3XX_ICM9_BASE UL(0xC0000000)
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/* ICM1 - Low speed connection */
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#define SPEAR3XX_ICM1_2_BASE 0xD0000000
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#define SPEAR3XX_ICM1_UART_BASE 0xD0000000
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#define SPEAR3XX_ICM1_2_BASE UL(0xD0000000)
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#define SPEAR3XX_ICM1_UART_BASE UL(0xD0000000)
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#define VA_SPEAR3XX_ICM1_UART_BASE IO_ADDRESS(SPEAR3XX_ICM1_UART_BASE)
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#define SPEAR3XX_ICM1_ADC_BASE 0xD0080000
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#define SPEAR3XX_ICM1_SSP_BASE 0xD0100000
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#define SPEAR3XX_ICM1_I2C_BASE 0xD0180000
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#define SPEAR3XX_ICM1_JPEG_BASE 0xD0800000
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#define SPEAR3XX_ICM1_IRDA_BASE 0xD1000000
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#define SPEAR3XX_ICM1_SRAM_BASE 0xD2800000
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#define SPEAR3XX_ICM1_ADC_BASE UL(0xD0080000)
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#define SPEAR3XX_ICM1_SSP_BASE UL(0xD0100000)
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#define SPEAR3XX_ICM1_I2C_BASE UL(0xD0180000)
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#define SPEAR3XX_ICM1_JPEG_BASE UL(0xD0800000)
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#define SPEAR3XX_ICM1_IRDA_BASE UL(0xD1000000)
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#define SPEAR3XX_ICM1_SRAM_BASE UL(0xD2800000)
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/* ICM2 - Application Subsystem */
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#define SPEAR3XX_ICM2_HWACCEL0_BASE 0xD8800000
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#define SPEAR3XX_ICM2_HWACCEL1_BASE 0xD9000000
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#define SPEAR3XX_ICM2_HWACCEL0_BASE UL(0xD8800000)
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#define SPEAR3XX_ICM2_HWACCEL1_BASE UL(0xD9000000)
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/* ICM4 - High Speed Connection */
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#define SPEAR3XX_ICM4_BASE 0xE0000000
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#define SPEAR3XX_ICM4_MII_BASE 0xE0800000
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#define SPEAR3XX_ICM4_USBD_FIFO_BASE 0xE1000000
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#define SPEAR3XX_ICM4_USBD_CSR_BASE 0xE1100000
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#define SPEAR3XX_ICM4_USBD_PLDT_BASE 0xE1200000
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#define SPEAR3XX_ICM4_USB_EHCI0_1_BASE 0xE1800000
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#define SPEAR3XX_ICM4_USB_OHCI0_BASE 0xE1900000
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#define SPEAR3XX_ICM4_USB_OHCI1_BASE 0xE2100000
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#define SPEAR3XX_ICM4_USB_ARB_BASE 0xE2800000
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#define SPEAR3XX_ICM4_BASE UL(0xE0000000)
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#define SPEAR3XX_ICM4_MII_BASE UL(0xE0800000)
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#define SPEAR3XX_ICM4_USBD_FIFO_BASE UL(0xE1000000)
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#define SPEAR3XX_ICM4_USBD_CSR_BASE UL(0xE1100000)
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#define SPEAR3XX_ICM4_USBD_PLDT_BASE UL(0xE1200000)
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#define SPEAR3XX_ICM4_USB_EHCI0_1_BASE UL(0xE1800000)
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#define SPEAR3XX_ICM4_USB_OHCI0_BASE UL(0xE1900000)
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#define SPEAR3XX_ICM4_USB_OHCI1_BASE UL(0xE2100000)
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#define SPEAR3XX_ICM4_USB_ARB_BASE UL(0xE2800000)
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/* ML1 - Multi Layer CPU Subsystem */
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#define SPEAR3XX_ICM3_ML1_2_BASE 0xF0000000
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#define SPEAR3XX_ML1_TMR_BASE 0xF0000000
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#define SPEAR3XX_ML1_VIC_BASE 0xF1100000
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#define SPEAR3XX_ICM3_ML1_2_BASE UL(0xF0000000)
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#define SPEAR3XX_ML1_TMR_BASE UL(0xF0000000)
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#define SPEAR3XX_ML1_VIC_BASE UL(0xF1100000)
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#define VA_SPEAR3XX_ML1_VIC_BASE IO_ADDRESS(SPEAR3XX_ML1_VIC_BASE)
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/* ICM3 - Basic Subsystem */
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#define SPEAR3XX_ICM3_SMEM_BASE 0xF8000000
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#define SPEAR3XX_ICM3_SMI_CTRL_BASE 0xFC000000
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#define SPEAR3XX_ICM3_DMA_BASE 0xFC400000
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#define SPEAR3XX_ICM3_SDRAM_CTRL_BASE 0xFC600000
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#define SPEAR3XX_ICM3_TMR0_BASE 0xFC800000
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#define SPEAR3XX_ICM3_WDT_BASE 0xFC880000
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#define SPEAR3XX_ICM3_RTC_BASE 0xFC900000
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#define SPEAR3XX_ICM3_GPIO_BASE 0xFC980000
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#define SPEAR3XX_ICM3_SYS_CTRL_BASE 0xFCA00000
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#define SPEAR3XX_ICM3_SMEM_BASE UL(0xF8000000)
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#define SPEAR3XX_ICM3_SMI_CTRL_BASE UL(0xFC000000)
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#define SPEAR3XX_ICM3_DMA_BASE UL(0xFC400000)
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#define SPEAR3XX_ICM3_SDRAM_CTRL_BASE UL(0xFC600000)
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#define SPEAR3XX_ICM3_TMR0_BASE UL(0xFC800000)
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#define SPEAR3XX_ICM3_WDT_BASE UL(0xFC880000)
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#define SPEAR3XX_ICM3_RTC_BASE UL(0xFC900000)
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#define SPEAR3XX_ICM3_GPIO_BASE UL(0xFC980000)
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#define SPEAR3XX_ICM3_SYS_CTRL_BASE UL(0xFCA00000)
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#define VA_SPEAR3XX_ICM3_SYS_CTRL_BASE IO_ADDRESS(SPEAR3XX_ICM3_SYS_CTRL_BASE)
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#define SPEAR3XX_ICM3_MISC_REG_BASE 0xFCA80000
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#define SPEAR3XX_ICM3_MISC_REG_BASE UL(0xFCA80000)
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#define VA_SPEAR3XX_ICM3_MISC_REG_BASE IO_ADDRESS(SPEAR3XX_ICM3_MISC_REG_BASE)
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#define SPEAR3XX_ICM3_TMR1_BASE 0xFCB00000
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#define SPEAR3XX_ICM3_TMR1_BASE UL(0xFCB00000)
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/* Debug uart for linux, will be used for debug and uncompress messages */
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#define SPEAR_DBG_UART_BASE SPEAR3XX_ICM1_UART_BASE
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@ -17,7 +17,7 @@
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#define __MACH_SPEAR300_H
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/* Base address of various IPs */
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#define SPEAR300_TELECOM_BASE 0x50000000
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#define SPEAR300_TELECOM_BASE UL(0x50000000)
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/* Interrupt registers offsets and masks */
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#define INT_ENB_MASK_REG 0x54
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@ -34,20 +34,20 @@
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#define SHIRQ_RAS1_MASK 0x1FF
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#define SPEAR300_CLCD_BASE 0x60000000
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#define SPEAR300_SDHCI_BASE 0x70000000
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#define SPEAR300_NAND_0_BASE 0x80000000
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#define SPEAR300_NAND_1_BASE 0x84000000
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#define SPEAR300_NAND_2_BASE 0x88000000
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#define SPEAR300_NAND_3_BASE 0x8c000000
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#define SPEAR300_NOR_0_BASE 0x90000000
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#define SPEAR300_NOR_1_BASE 0x91000000
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#define SPEAR300_NOR_2_BASE 0x92000000
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#define SPEAR300_NOR_3_BASE 0x93000000
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#define SPEAR300_FSMC_BASE 0x94000000
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#define SPEAR300_SOC_CONFIG_BASE 0x99000000
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#define SPEAR300_KEYBOARD_BASE 0xA0000000
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#define SPEAR300_GPIO_BASE 0xA9000000
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#define SPEAR300_CLCD_BASE UL(0x60000000)
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#define SPEAR300_SDHCI_BASE UL(0x70000000)
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#define SPEAR300_NAND_0_BASE UL(0x80000000)
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#define SPEAR300_NAND_1_BASE UL(0x84000000)
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#define SPEAR300_NAND_2_BASE UL(0x88000000)
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#define SPEAR300_NAND_3_BASE UL(0x8c000000)
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#define SPEAR300_NOR_0_BASE UL(0x90000000)
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#define SPEAR300_NOR_1_BASE UL(0x91000000)
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#define SPEAR300_NOR_2_BASE UL(0x92000000)
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#define SPEAR300_NOR_3_BASE UL(0x93000000)
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#define SPEAR300_FSMC_BASE UL(0x94000000)
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#define SPEAR300_SOC_CONFIG_BASE UL(0x99000000)
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#define SPEAR300_KEYBOARD_BASE UL(0xA0000000)
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#define SPEAR300_GPIO_BASE UL(0xA9000000)
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#endif /* __MACH_SPEAR300_H */
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@ -16,17 +16,17 @@
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#ifndef __MACH_SPEAR310_H
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#define __MACH_SPEAR310_H
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#define SPEAR310_NAND_BASE 0x40000000
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#define SPEAR310_FSMC_BASE 0x44000000
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#define SPEAR310_UART1_BASE 0xB2000000
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#define SPEAR310_UART2_BASE 0xB2080000
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#define SPEAR310_UART3_BASE 0xB2100000
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#define SPEAR310_UART4_BASE 0xB2180000
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#define SPEAR310_UART5_BASE 0xB2200000
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#define SPEAR310_HDLC_BASE 0xB2800000
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#define SPEAR310_RS485_0_BASE 0xB3000000
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#define SPEAR310_RS485_1_BASE 0xB3800000
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#define SPEAR310_SOC_CONFIG_BASE 0xB4000000
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#define SPEAR310_NAND_BASE UL(0x40000000)
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#define SPEAR310_FSMC_BASE UL(0x44000000)
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#define SPEAR310_UART1_BASE UL(0xB2000000)
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#define SPEAR310_UART2_BASE UL(0xB2080000)
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#define SPEAR310_UART3_BASE UL(0xB2100000)
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#define SPEAR310_UART4_BASE UL(0xB2180000)
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#define SPEAR310_UART5_BASE UL(0xB2200000)
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#define SPEAR310_HDLC_BASE UL(0xB2800000)
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#define SPEAR310_RS485_0_BASE UL(0xB3000000)
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#define SPEAR310_RS485_1_BASE UL(0xB3800000)
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#define SPEAR310_SOC_CONFIG_BASE UL(0xB4000000)
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/* Interrupt registers offsets and masks */
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#define INT_STS_MASK_REG 0x04
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@ -16,23 +16,24 @@
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#ifndef __MACH_SPEAR320_H
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#define __MACH_SPEAR320_H
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#define SPEAR320_EMI_CTRL_BASE 0x40000000
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#define SPEAR320_FSMC_BASE 0x4C000000
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#define SPEAR320_I2S_BASE 0x60000000
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#define SPEAR320_SDHCI_BASE 0x70000000
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#define SPEAR320_CLCD_BASE 0x90000000
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#define SPEAR320_PAR_PORT_BASE 0xA0000000
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#define SPEAR320_CAN0_BASE 0xA1000000
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#define SPEAR320_CAN1_BASE 0xA2000000
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#define SPEAR320_UART1_BASE 0xA3000000
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#define SPEAR320_UART2_BASE 0xA4000000
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#define SPEAR320_SSP0_BASE 0xA5000000
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#define SPEAR320_SSP1_BASE 0xA6000000
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#define SPEAR320_I2C_BASE 0xA7000000
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#define SPEAR320_PWM_BASE 0xA8000000
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#define SPEAR320_SMII0_BASE 0xAA000000
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#define SPEAR320_SMII1_BASE 0xAB000000
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#define SPEAR320_SOC_CONFIG_BASE 0xB3000000
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#define SPEAR320_EMI_CTRL_BASE UL(0x40000000)
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#define SPEAR320_FSMC_BASE UL(0x4C000000)
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#define SPEAR320_NAND_BASE UL(0x50000000)
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#define SPEAR320_I2S_BASE UL(0x60000000)
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#define SPEAR320_SDHCI_BASE UL(0x70000000)
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#define SPEAR320_CLCD_BASE UL(0x90000000)
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#define SPEAR320_PAR_PORT_BASE UL(0xA0000000)
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#define SPEAR320_CAN0_BASE UL(0xA1000000)
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#define SPEAR320_CAN1_BASE UL(0xA2000000)
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#define SPEAR320_UART1_BASE UL(0xA3000000)
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#define SPEAR320_UART2_BASE UL(0xA4000000)
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#define SPEAR320_SSP0_BASE UL(0xA5000000)
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#define SPEAR320_SSP1_BASE UL(0xA6000000)
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#define SPEAR320_I2C_BASE UL(0xA7000000)
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#define SPEAR320_PWM_BASE UL(0xA8000000)
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#define SPEAR320_SMII0_BASE UL(0xAA000000)
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#define SPEAR320_SMII1_BASE UL(0xAB000000)
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#define SPEAR320_SOC_CONFIG_BASE UL(0xB3000000)
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/* Interrupt registers offsets and masks */
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#define INT_STS_MASK_REG 0x04
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#ifndef __MACH_SPEAR6XX_H
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#define __MACH_SPEAR6XX_H
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#include <asm/memory.h>
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#include <mach/spear600.h>
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#define SPEAR6XX_ML_SDRAM_BASE 0x00000000
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#define SPEAR6XX_ML_SDRAM_BASE UL(0x00000000)
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/* ICM1 - Low speed connection */
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#define SPEAR6XX_ICM1_BASE 0xD0000000
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#define SPEAR6XX_ICM1_BASE UL(0xD0000000)
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#define SPEAR6XX_ICM1_UART0_BASE 0xD0000000
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#define SPEAR6XX_ICM1_UART0_BASE UL(0xD0000000)
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#define VA_SPEAR6XX_ICM1_UART0_BASE IO_ADDRESS(SPEAR6XX_ICM1_UART0_BASE)
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#define SPEAR6XX_ICM1_UART1_BASE 0xD0080000
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#define SPEAR6XX_ICM1_SSP0_BASE 0xD0100000
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#define SPEAR6XX_ICM1_SSP1_BASE 0xD0180000
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#define SPEAR6XX_ICM1_I2C_BASE 0xD0200000
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#define SPEAR6XX_ICM1_JPEG_BASE 0xD0800000
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#define SPEAR6XX_ICM1_IRDA_BASE 0xD1000000
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#define SPEAR6XX_ICM1_FSMC_BASE 0xD1800000
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#define SPEAR6XX_ICM1_NAND_BASE 0xD2000000
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#define SPEAR6XX_ICM1_SRAM_BASE 0xD2800000
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#define SPEAR6XX_ICM1_UART1_BASE UL(0xD0080000)
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#define SPEAR6XX_ICM1_SSP0_BASE UL(0xD0100000)
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#define SPEAR6XX_ICM1_SSP1_BASE UL(0xD0180000)
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#define SPEAR6XX_ICM1_I2C_BASE UL(0xD0200000)
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#define SPEAR6XX_ICM1_JPEG_BASE UL(0xD0800000)
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#define SPEAR6XX_ICM1_IRDA_BASE UL(0xD1000000)
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#define SPEAR6XX_ICM1_FSMC_BASE UL(0xD1800000)
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#define SPEAR6XX_ICM1_NAND_BASE UL(0xD2000000)
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#define SPEAR6XX_ICM1_SRAM_BASE UL(0xD2800000)
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/* ICM2 - Application Subsystem */
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#define SPEAR6XX_ICM2_BASE 0xD8000000
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#define SPEAR6XX_ICM2_TMR0_BASE 0xD8000000
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#define SPEAR6XX_ICM2_TMR1_BASE 0xD8080000
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#define SPEAR6XX_ICM2_GPIO_BASE 0xD8100000
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#define SPEAR6XX_ICM2_SPI2_BASE 0xD8180000
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#define SPEAR6XX_ICM2_ADC_BASE 0xD8200000
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#define SPEAR6XX_ICM2_BASE UL(0xD8000000)
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#define SPEAR6XX_ICM2_TMR0_BASE UL(0xD8000000)
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#define SPEAR6XX_ICM2_TMR1_BASE UL(0xD8080000)
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#define SPEAR6XX_ICM2_GPIO_BASE UL(0xD8100000)
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#define SPEAR6XX_ICM2_SSP2_BASE UL(0xD8180000)
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#define SPEAR6XX_ICM2_ADC_BASE UL(0xD8200000)
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/* ML-1, 2 - Multi Layer CPU Subsystem */
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#define SPEAR6XX_ML_CPU_BASE 0xF0000000
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#define SPEAR6XX_CPU_TMR_BASE 0xF0000000
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#define SPEAR6XX_CPU_GPIO_BASE 0xF0100000
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#define SPEAR6XX_CPU_VIC_SEC_BASE 0xF1000000
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#define SPEAR6XX_ML_CPU_BASE UL(0xF0000000)
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#define SPEAR6XX_CPU_TMR_BASE UL(0xF0000000)
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#define SPEAR6XX_CPU_GPIO_BASE UL(0xF0100000)
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#define SPEAR6XX_CPU_VIC_SEC_BASE UL(0xF1000000)
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#define VA_SPEAR6XX_CPU_VIC_SEC_BASE IO_ADDRESS(SPEAR6XX_CPU_VIC_SEC_BASE)
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#define SPEAR6XX_CPU_VIC_PRI_BASE 0xF1100000
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#define SPEAR6XX_CPU_VIC_PRI_BASE UL(0xF1100000)
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#define VA_SPEAR6XX_CPU_VIC_PRI_BASE IO_ADDRESS(SPEAR6XX_CPU_VIC_PRI_BASE)
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/* ICM3 - Basic Subsystem */
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#define SPEAR6XX_ICM3_BASE 0xF8000000
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#define SPEAR6XX_ICM3_SMEM_BASE 0xF8000000
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#define SPEAR6XX_ICM3_SMI_CTRL_BASE 0xFC000000
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#define SPEAR6XX_ICM3_CLCD_BASE 0xFC200000
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#define SPEAR6XX_ICM3_DMA_BASE 0xFC400000
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#define SPEAR6XX_ICM3_SDRAM_CTRL_BASE 0xFC600000
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#define SPEAR6XX_ICM3_TMR_BASE 0xFC800000
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#define SPEAR6XX_ICM3_WDT_BASE 0xFC880000
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#define SPEAR6XX_ICM3_RTC_BASE 0xFC900000
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#define SPEAR6XX_ICM3_GPIO_BASE 0xFC980000
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#define SPEAR6XX_ICM3_SYS_CTRL_BASE 0xFCA00000
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#define SPEAR6XX_ICM3_BASE UL(0xF8000000)
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#define SPEAR6XX_ICM3_SMEM_BASE UL(0xF8000000)
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#define SPEAR6XX_ICM3_SMI_CTRL_BASE UL(0xFC000000)
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#define SPEAR6XX_ICM3_CLCD_BASE UL(0xFC200000)
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#define SPEAR6XX_ICM3_DMA_BASE UL(0xFC400000)
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#define SPEAR6XX_ICM3_SDRAM_CTRL_BASE UL(0xFC600000)
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#define SPEAR6XX_ICM3_TMR_BASE UL(0xFC800000)
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#define SPEAR6XX_ICM3_WDT_BASE UL(0xFC880000)
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#define SPEAR6XX_ICM3_RTC_BASE UL(0xFC900000)
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#define SPEAR6XX_ICM3_GPIO_BASE UL(0xFC980000)
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#define SPEAR6XX_ICM3_SYS_CTRL_BASE UL(0xFCA00000)
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#define VA_SPEAR6XX_ICM3_SYS_CTRL_BASE IO_ADDRESS(SPEAR6XX_ICM3_SYS_CTRL_BASE)
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#define SPEAR6XX_ICM3_MISC_REG_BASE 0xFCA80000
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#define SPEAR6XX_ICM3_MISC_REG_BASE UL(0xFCA80000)
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#define VA_SPEAR6XX_ICM3_MISC_REG_BASE IO_ADDRESS(SPEAR6XX_ICM3_MISC_REG_BASE)
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/* ICM4 - High Speed Connection */
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#define SPEAR6XX_ICM4_BASE 0xE0000000
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#define SPEAR6XX_ICM4_GMAC_BASE 0xE0800000
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#define SPEAR6XX_ICM4_USBD_FIFO_BASE 0xE1000000
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#define SPEAR6XX_ICM4_USBD_CSR_BASE 0xE1100000
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#define SPEAR6XX_ICM4_USBD_PLDT_BASE 0xE1200000
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#define SPEAR6XX_ICM4_USB_EHCI0_BASE 0xE1800000
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#define SPEAR6XX_ICM4_USB_OHCI0_BASE 0xE1900000
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#define SPEAR6XX_ICM4_USB_EHCI1_BASE 0xE2000000
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#define SPEAR6XX_ICM4_USB_OHCI1_BASE 0xE2100000
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#define SPEAR6XX_ICM4_USB_ARB_BASE 0xE2800000
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#define SPEAR6XX_ICM4_BASE UL(0xE0000000)
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#define SPEAR6XX_ICM4_GMAC_BASE UL(0xE0800000)
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#define SPEAR6XX_ICM4_USBD_FIFO_BASE UL(0xE1000000)
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#define SPEAR6XX_ICM4_USBD_CSR_BASE UL(0xE1100000)
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#define SPEAR6XX_ICM4_USBD_PLDT_BASE UL(0xE1200000)
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#define SPEAR6XX_ICM4_USB_EHCI0_BASE UL(0xE1800000)
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#define SPEAR6XX_ICM4_USB_OHCI0_BASE UL(0xE1900000)
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#define SPEAR6XX_ICM4_USB_EHCI1_BASE UL(0xE2000000)
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#define SPEAR6XX_ICM4_USB_OHCI1_BASE UL(0xE2100000)
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#define SPEAR6XX_ICM4_USB_ARB_BASE UL(0xE2800000)
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/* Debug uart for linux, will be used for debug and uncompress messages */
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#define SPEAR_DBG_UART_BASE SPEAR6XX_ICM1_UART0_BASE
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|
|
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Loading…
Reference in a new issue