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ARM: zynq: add gem support

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The zynq includes a Cadence GEM IP core. This is compatible with the macb driver.
Add it to the zynq-7000 DT.

Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Josh Cartwright <josh.cartwright@ni.com>
[soren: rebased to current Linus tree, added zc706 + zed support, moved phy-mode property to board level dtses]
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This commit is contained in:
Steffen Trumtrar 2013-12-11 09:29:49 -08:00 committed by Michal Simek
parent dc1ccc4815
commit 982264c3e0
4 changed files with 33 additions and 0 deletions
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18
arch/arm/boot/dts/zynq-7000.dtsi
View file

@ -65,6 +65,24 @@ uart1: uart@e0001000 {
interrupts = <0 50 4>;
};
gem0: ethernet@e000b000 {
compatible = "cdns,gem";
reg = <0xe000b000 0x4000>;
status = "disabled";
interrupts = <0 22 4>;
clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>;
clock-names = "pclk", "hclk", "tx_clk";
};
gem1: ethernet@e000c000 {
compatible = "cdns,gem";
reg = <0xe000c000 0x4000>;
status = "disabled";
interrupts = <0 45 4>;
clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>;
clock-names = "pclk", "hclk", "tx_clk";
};
slcr: slcr@f8000000 {
compatible = "xlnx,zynq-slcr";
reg = <0xF8000000 0x1000>;

5
arch/arm/boot/dts/zynq-zc702.dts
View file

@ -29,6 +29,11 @@ chosen {
};
&gem0 {
status = "okay";
phy-mode = "rgmii";
};
&uart1 {
status = "okay";
};

5
arch/arm/boot/dts/zynq-zc706.dts
View file

@ -30,6 +30,11 @@ chosen {
};
&gem0 {
status = "okay";
phy-mode = "rgmii";
};
&uart1 {
status = "okay";
};

5
arch/arm/boot/dts/zynq-zed.dts
View file

@ -30,6 +30,11 @@ chosen {
};
&gem0 {
status = "okay";
phy-mode = "rgmii";
};
&uart1 {
status = "okay";
};