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ARM: dts: calxeda: move memory-controller node out of ecx-common.dtsi
The DDR controller is slightly different in ECX-2000 and ECX-1000, so we need to have different nodes for each platform. Signed-off-by: Rob Herring <rob.herring@calxeda.com> [Device Tree documentation updated.] Signed-off-by: Robert Richter <rric@kernel.org>
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commit
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4 changed files with 15 additions and 7 deletions
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@ -1,7 +1,9 @@
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Calxeda DDR memory controller
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Calxeda DDR memory controller
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Properties:
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Properties:
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- compatible : Should be "calxeda,hb-ddr-ctrl"
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- compatible : Should be:
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- "calxeda,hb-ddr-ctrl" for ECX-1000
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- "calxeda,ecx-2000-ddr-ctrl" for ECX-2000
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- reg : Address and size for DDR controller registers.
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- reg : Address and size for DDR controller registers.
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- interrupts : Interrupt for DDR controller.
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- interrupts : Interrupt for DDR controller.
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@ -85,6 +85,12 @@ timer {
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<1 10 0xf08>;
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<1 10 0xf08>;
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};
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};
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memory-controller@fff00000 {
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compatible = "calxeda,ecx-2000-ddr-ctrl";
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reg = <0xfff00000 0x1000>;
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interrupts = <0 91 4>;
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};
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intc: interrupt-controller@fff11000 {
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intc: interrupt-controller@fff11000 {
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compatible = "arm,cortex-a15-gic";
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compatible = "arm,cortex-a15-gic";
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#interrupt-cells = <3>;
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#interrupt-cells = <3>;
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@ -45,12 +45,6 @@ sdhci@ffe0e000 {
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status = "disabled";
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status = "disabled";
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};
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};
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memory-controller@fff00000 {
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compatible = "calxeda,hb-ddr-ctrl";
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reg = <0xfff00000 0x1000>;
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interrupts = <0 91 4>;
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};
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ipc@fff20000 {
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ipc@fff20000 {
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compatible = "arm,pl320", "arm,primecell";
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compatible = "arm,pl320", "arm,primecell";
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reg = <0xfff20000 0x1000>;
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reg = <0xfff20000 0x1000>;
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@ -86,6 +86,12 @@ memory {
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soc {
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soc {
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ranges = <0x00000000 0x00000000 0xffffffff>;
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ranges = <0x00000000 0x00000000 0xffffffff>;
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memory-controller@fff00000 {
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compatible = "calxeda,hb-ddr-ctrl";
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reg = <0xfff00000 0x1000>;
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interrupts = <0 91 4>;
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};
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timer@fff10600 {
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timer@fff10600 {
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compatible = "arm,cortex-a9-twd-timer";
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compatible = "arm,cortex-a9-twd-timer";
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reg = <0xfff10600 0x20>;
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reg = <0xfff10600 0x20>;
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