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drm/amd/display: Update bounding box values for DCN321
[Why&how]
Update bounding box values as per hardware spec
Fixes: 197485c695
("drm/amd/display: Create dcn321_fpu file")
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
parent
99d92eaca5
commit
989cd3e76a
1 changed files with 12 additions and 12 deletions
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@ -106,16 +106,16 @@ struct _vcs_dpi_soc_bounding_box_st dcn3_21_soc = {
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.clock_limits = {
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{
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.state = 0,
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.dcfclk_mhz = 1564.0,
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.fabricclk_mhz = 400.0,
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.dispclk_mhz = 2150.0,
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.dppclk_mhz = 2150.0,
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.dcfclk_mhz = 1434.0,
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.fabricclk_mhz = 2250.0,
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.dispclk_mhz = 1720.0,
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.dppclk_mhz = 1720.0,
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.phyclk_mhz = 810.0,
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.phyclk_d18_mhz = 667.0,
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.phyclk_d32_mhz = 625.0,
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.phyclk_d32_mhz = 313.0,
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.socclk_mhz = 1200.0,
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.dscclk_mhz = 716.667,
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.dram_speed_mts = 1600.0,
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.dscclk_mhz = 573.333,
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.dram_speed_mts = 16000.0,
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.dtbclk_mhz = 1564.0,
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},
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},
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@ -125,14 +125,14 @@ struct _vcs_dpi_soc_bounding_box_st dcn3_21_soc = {
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.sr_exit_z8_time_us = 285.0,
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.sr_enter_plus_exit_z8_time_us = 320,
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.writeback_latency_us = 12.0,
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.round_trip_ping_latency_dcfclk_cycles = 263,
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.round_trip_ping_latency_dcfclk_cycles = 207,
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.urgent_latency_pixel_data_only_us = 4,
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.urgent_latency_pixel_mixed_with_vm_data_us = 4,
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.urgent_latency_vm_data_only_us = 4,
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.fclk_change_latency_us = 20,
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.usr_retraining_latency_us = 2,
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.smn_latency_us = 2,
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.mall_allocated_for_dcn_mbytes = 64,
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.fclk_change_latency_us = 7,
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.usr_retraining_latency_us = 0,
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.smn_latency_us = 0,
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.mall_allocated_for_dcn_mbytes = 32,
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.urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,
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.urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,
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.urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,
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