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ARM: multi_v7_defconfig: Enable s5p-secss driver

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The Exynos SoC provides a Security SubSystem block for accelerating some
cryptographic operations.  Enable the driver for it - s5p-secss to
utilize the hardware acceleration.

Currently the s5p-secss driver supports AES in CBC and ECB modes.
However its usefulness could be doubted. Excerpt of tests on Odroid XU3
(Exynos5422), for 256 bit key, encryption, performance CPU freq governor:

  algorithm        | block size [b] | average speed [MB/s] |
  cbc-aes-s5p      |             16 |                 11.5 |
  cbc-aes-s5p      |             64 |                 25.4 |
  cbc-aes-s5p      |            256 |                 41.0 |
  cbc-aes-s5p      |           1024 |                 47.4 |
  cbc-aes-s5p      |           8192 |                 49.0 |
  cbc(aes-generic) |             16 |                  0.4 |
  cbc(aes-generic) |             64 |                  1.8 |
  cbc(aes-generic) |            256 |                  6.6 |
  cbc(aes-generic) |           1024 |                 25.2 |
  cbc(aes-generic) |           8192 |                 83.1 |

Anyway enable the driver so it will get some testing coverage by
community.

Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
This commit is contained in:
Krzysztof Kozlowski 2016-06-02 07:55:15 +02:00
parent d649ca0097
commit 98b927bb0c
1 changed files with 1 additions and 0 deletions
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1
arch/arm/configs/multi_v7_defconfig
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@ -873,6 +873,7 @@ CONFIG_KEYSTONE_IRQ=y
CONFIG_HW_RANDOM=y
CONFIG_HW_RANDOM_ST=y
CONFIG_CRYPTO_DEV_MARVELL_CESA=m
CONFIG_CRYPTO_DEV_S5P=m
CONFIG_CRYPTO_DEV_SUN4I_SS=m
CONFIG_CRYPTO_DEV_ROCKCHIP=m
CONFIG_ARM_CRYPTO=y