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Add Chameleon v3 ASoC audio

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Merge series from Paweł Anikiel <pan@semihalf.com>:

The Google Chameleon v3 is a device made for testing audio and video
paths of other devices. This patchset adds support for ASoC audio on
this device. It has two audio sources: HDMI audio from the it68051 chip
(RX only), and analog audio from the ssm2603 chip (RX and TX).

The patchset adds the ASoC platform and codec drivers.
This commit is contained in:
Mark Brown 2023-05-19 07:27:08 +09:00
commit 98be58f2b5
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GPG key ID: 24D68B725D5487D0
10 changed files with 474 additions and 0 deletions
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31
Documentation/devicetree/bindings/sound/google,chv3-codec.yaml Normal file
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@ -0,0 +1,31 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/sound/google,chv3-codec.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Google Chameleon v3 audio codec
maintainers:
- Paweł Anikiel <pan@semihalf.com>
allOf:
- $ref: dai-common.yaml#
properties:
compatible:
const: google,chv3-codec
"#sound-dai-cells":
const: 0
required:
- compatible
additionalProperties: false
examples:
- |
audio-codec {
compatible = "google,chv3-codec";
};

44
Documentation/devicetree/bindings/sound/google,chv3-i2s.yaml Normal file
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@ -0,0 +1,44 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/sound/google,chv3-i2s.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Google Chameleon v3 I2S device
maintainers:
- Paweł Anikiel <pan@semihalf.com>
description: |
I2S device for the Google Chameleon v3. The device handles both RX
and TX using a producer/consumer ring buffer design.
properties:
compatible:
const: google,chv3-i2s
reg:
items:
- description: core registers
- description: irq registers
interrupts:
maxItems: 1
required:
- compatible
- reg
- interrupts
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
i2s@c0060300 {
compatible = "google,chv3-i2s";
reg = <0xc0060300 0x100>,
<0xc0060f00 0x10>;
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
};

1
sound/soc/Kconfig
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@ -75,6 +75,7 @@ source "sound/soc/bcm/Kconfig"
source "sound/soc/cirrus/Kconfig"
source "sound/soc/dwc/Kconfig"
source "sound/soc/fsl/Kconfig"
source "sound/soc/google/Kconfig"
source "sound/soc/hisilicon/Kconfig"
source "sound/soc/jz4740/Kconfig"
source "sound/soc/kirkwood/Kconfig"

1
sound/soc/Makefile
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@ -43,6 +43,7 @@ obj-$(CONFIG_SND_SOC) += bcm/
obj-$(CONFIG_SND_SOC) += cirrus/
obj-$(CONFIG_SND_SOC) += dwc/
obj-$(CONFIG_SND_SOC) += fsl/
obj-$(CONFIG_SND_SOC) += google/
obj-$(CONFIG_SND_SOC) += hisilicon/
obj-$(CONFIG_SND_SOC) += jz4740/
obj-$(CONFIG_SND_SOC) += img/

8
sound/soc/codecs/Kconfig
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@ -57,6 +57,7 @@ config SND_SOC_ALL_CODECS
imply SND_SOC_AW88395
imply SND_SOC_BT_SCO
imply SND_SOC_BD28623
imply SND_SOC_CHV3_CODEC
imply SND_SOC_CQ0093VC
imply SND_SOC_CROS_EC_CODEC
imply SND_SOC_CS35L32
@ -644,6 +645,13 @@ config SND_SOC_BD28623
config SND_SOC_BT_SCO
tristate "Dummy BT SCO codec driver"
config SND_SOC_CHV3_CODEC
tristate "Google Chameleon v3 codec driver"
help
Enable support for the Google Chameleon v3 audio codec.
This codec does not have a control interface, it always outputs
8 channel S32_LE audio.
config SND_SOC_CPCAP
tristate "Motorola CPCAP codec"
depends on MFD_CPCAP || COMPILE_TEST

2
sound/soc/codecs/Makefile
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@ -51,6 +51,7 @@ snd-soc-aw88395-objs := aw88395/aw88395.o \
aw88395/aw88395_device.o
snd-soc-bd28623-objs := bd28623.o
snd-soc-bt-sco-objs := bt-sco.o
snd-soc-chv3-codec-objs := chv3-codec.o
snd-soc-cpcap-objs := cpcap.o
snd-soc-cq93vc-objs := cq93vc.o
snd-soc-cros-ec-codec-objs := cros_ec_codec.o
@ -427,6 +428,7 @@ obj-$(CONFIG_SND_SOC_AW88395_LIB) += snd-soc-aw88395-lib.o
obj-$(CONFIG_SND_SOC_AW88395) +=snd-soc-aw88395.o
obj-$(CONFIG_SND_SOC_BD28623) += snd-soc-bd28623.o
obj-$(CONFIG_SND_SOC_BT_SCO) += snd-soc-bt-sco.o
obj-$(CONFIG_SND_SOC_CHV3_CODEC) += snd-soc-chv3-codec.o
obj-$(CONFIG_SND_SOC_CQ0093VC) += snd-soc-cq93vc.o
obj-$(CONFIG_SND_SOC_CPCAP) += snd-soc-cpcap.o
obj-$(CONFIG_SND_SOC_CROS_EC_CODEC) += snd-soc-cros-ec-codec.o

41
sound/soc/codecs/chv3-codec.c Normal file
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@ -0,0 +1,41 @@
// SPDX-License-Identifier: GPL-2.0-only
#include <linux/module.h>
#include <sound/soc.h>
static struct snd_soc_dai_driver chv3_codec_dai = {
.name = "chv3-codec-hifi",
.capture = {
.stream_name = "Capture",
.channels_min = 8,
.channels_max = 8,
.rates = SNDRV_PCM_RATE_CONTINUOUS,
.formats = SNDRV_PCM_FMTBIT_S32_LE,
},
};
static const struct snd_soc_component_driver soc_component_dev_chv3_codec = {
};
static int chv3_codec_probe(struct platform_device *pdev)
{
return devm_snd_soc_register_component(&pdev->dev,
&soc_component_dev_chv3_codec, &chv3_codec_dai, 1);
}
static const struct of_device_id chv3_codec_of_match[] = {
{ .compatible = "google,chv3-codec", },
{ }
};
static struct platform_driver chv3_codec_platform_driver = {
.driver = {
.name = "chv3-codec",
.of_match_table = chv3_codec_of_match,
},
.probe = chv3_codec_probe,
};
module_platform_driver(chv3_codec_platform_driver);
MODULE_DESCRIPTION("ASoC Chameleon v3 codec driver");
MODULE_AUTHOR("Pawel Anikiel <pan@semihalf.com>");
MODULE_LICENSE("GPL");

6
sound/soc/google/Kconfig Normal file
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@ -0,0 +1,6 @@
# SPDX-License-Identifier: GPL-2.0-only
config SND_SOC_CHV3_I2S
tristate "Google Chameleon v3 I2S device"
help
Enable support for the Google Chameleon v3 I2S device.

2
sound/soc/google/Makefile Normal file
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@ -0,0 +1,2 @@
# SPDX-License-Identifier: GPL-2.0-only
obj-$(CONFIG_SND_SOC_CHV3_I2S) += chv3-i2s.o

338
sound/soc/google/chv3-i2s.c Normal file
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@ -0,0 +1,338 @@
// SPDX-License-Identifier: GPL-2.0-only
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <sound/soc.h>
/*
* The I2S interface consists of two ring buffers - one for RX and one for
* TX. A ring buffer has a producer index and a consumer index. Depending
* on which way the data is flowing, either the software or the hardware
* writes data and updates the producer index, and the other end reads data
* and updates the consumer index.
*
* The pointer managed by software is updated using the .ack callback
* (see chv3_dma_ack). This seems to be the only way to reliably obtain
* the appl_ptr from within the driver and pass it to hardware.
*
* Because of the two pointer design, the ring buffer can never be full. With
* capture this isn't a problem, because the hardware being the producer
* will wait for the consumer index to move out of the way. With playback,
* however, this is problematic, because ALSA wants to fill up the buffer
* completely when waiting for hardware. In the .ack callback, the driver
* would have to wait for the consumer index to move out of the way by
* busy-waiting, which would keep stalling the kernel for quite a long time.
*
* The workaround to this problem is to "lie" to ALSA that the hw_pointer
* is one frame behind what it actually is (see chv3_dma_pointer). This
* way, ALSA will not try to fill up the entire buffer, and all callbacks
* are wait-free.
*/
#define I2S_TX_ENABLE 0x00
#define I2S_TX_BASE_ADDR 0x04
#define I2S_TX_BUFFER_SIZE 0x08
#define I2S_TX_PRODUCER_IDX 0x0c
#define I2S_TX_CONSUMER_IDX 0x10
#define I2S_RX_ENABLE 0x14
#define I2S_RX_BASE_ADDR 0x18
#define I2S_RX_BUFFER_SIZE 0x1c
#define I2S_RX_PRODUCER_IDX 0x20
#define I2S_RX_CONSUMER_IDX 0x24
#define I2S_SOFT_RESET 0x2c
#define I2S_SOFT_RESET_RX_BIT 0x1
#define I2S_SOFT_RESET_TX_BIT 0x2
#define I2S_RX_IRQ 0x4c
#define I2S_RX_IRQ_CONST 0x50
#define I2S_TX_IRQ 0x54
#define I2S_TX_IRQ_CONST 0x58
#define I2S_IRQ_MASK 0x8
#define I2S_IRQ_CLR 0xc
#define I2S_IRQ_RX_BIT 0x1
#define I2S_IRQ_TX_BIT 0x2
#define I2S_MAX_BUFFER_SIZE 0x200000
struct chv3_i2s_dev {
struct device *dev;
void __iomem *iobase;
void __iomem *iobase_irq;
struct snd_pcm_substream *rx_substream;
struct snd_pcm_substream *tx_substream;
int tx_bytes_to_fetch;
};
static struct snd_soc_dai_driver chv3_i2s_dai = {
.name = "chv3-i2s",
.capture = {
.channels_min = 1,
.channels_max = 128,
.rates = SNDRV_PCM_RATE_CONTINUOUS,
.rate_min = 8000,
.rate_max = 96000,
.formats = SNDRV_PCM_FMTBIT_S32_LE,
},
.playback = {
.channels_min = 1,
.channels_max = 128,
.rates = SNDRV_PCM_RATE_CONTINUOUS,
.rate_min = 8000,
.rate_max = 96000,
.formats = SNDRV_PCM_FMTBIT_S32_LE,
},
};
static const struct snd_pcm_hardware chv3_dma_hw = {
.info = SNDRV_PCM_INFO_INTERLEAVED |
SNDRV_PCM_INFO_MMAP |
SNDRV_PCM_INFO_MMAP_VALID |
SNDRV_PCM_INFO_BLOCK_TRANSFER,
.buffer_bytes_max = I2S_MAX_BUFFER_SIZE,
.period_bytes_min = 64,
.period_bytes_max = 8192,
.periods_min = 4,
.periods_max = 256,
};
static inline void chv3_i2s_wr(struct chv3_i2s_dev *i2s, int offset, u32 val)
{
writel(val, i2s->iobase + offset);
}
static inline u32 chv3_i2s_rd(struct chv3_i2s_dev *i2s, int offset)
{
return readl(i2s->iobase + offset);
}
static irqreturn_t chv3_i2s_isr(int irq, void *data)
{
struct chv3_i2s_dev *i2s = data;
u32 reg;
reg = readl(i2s->iobase_irq + I2S_IRQ_CLR);
if (!reg)
return IRQ_NONE;
if (reg & I2S_IRQ_RX_BIT)
snd_pcm_period_elapsed(i2s->rx_substream);
if (reg & I2S_IRQ_TX_BIT)
snd_pcm_period_elapsed(i2s->tx_substream);
writel(reg, i2s->iobase_irq + I2S_IRQ_CLR);
return IRQ_HANDLED;
}
static int chv3_dma_open(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct chv3_i2s_dev *i2s = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
int res;
snd_soc_set_runtime_hwparams(substream, &chv3_dma_hw);
res = snd_pcm_hw_constraint_pow2(substream->runtime, 0,
SNDRV_PCM_HW_PARAM_BUFFER_BYTES);
if (res)
return res;
if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
i2s->rx_substream = substream;
else
i2s->tx_substream = substream;
return 0;
}
static int chv3_dma_close(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct chv3_i2s_dev *i2s = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
if (substream->pstr->stream == SNDRV_PCM_STREAM_CAPTURE)
chv3_i2s_wr(i2s, I2S_RX_ENABLE, 0);
else
chv3_i2s_wr(i2s, I2S_TX_ENABLE, 0);
return 0;
}
static int chv3_dma_pcm_construct(struct snd_soc_component *component,
struct snd_soc_pcm_runtime *rtd)
{
struct chv3_i2s_dev *i2s = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
struct snd_pcm_substream *substream;
int res;
substream = rtd->pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream;
if (substream) {
res = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, i2s->dev,
I2S_MAX_BUFFER_SIZE, &substream->dma_buffer);
if (res)
return res;
}
substream = rtd->pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream;
if (substream) {
res = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, i2s->dev,
I2S_MAX_BUFFER_SIZE, &substream->dma_buffer);
if (res)
return res;
}
return 0;
}
static int chv3_dma_hw_params(struct snd_soc_component *component,
struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
snd_pcm_set_runtime_buffer(substream, &substream->dma_buffer);
return 0;
}
static int chv3_dma_prepare(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct chv3_i2s_dev *i2s = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
unsigned int buffer_bytes, period_bytes, period_size;
buffer_bytes = snd_pcm_lib_buffer_bytes(substream);
period_bytes = snd_pcm_lib_period_bytes(substream);
period_size = substream->runtime->period_size;
if (substream->pstr->stream == SNDRV_PCM_STREAM_CAPTURE) {
chv3_i2s_wr(i2s, I2S_SOFT_RESET, I2S_SOFT_RESET_RX_BIT);
chv3_i2s_wr(i2s, I2S_RX_BASE_ADDR, substream->dma_buffer.addr);
chv3_i2s_wr(i2s, I2S_RX_BUFFER_SIZE, buffer_bytes);
chv3_i2s_wr(i2s, I2S_RX_IRQ, (period_size << 8) | 1);
chv3_i2s_wr(i2s, I2S_RX_ENABLE, 1);
} else {
chv3_i2s_wr(i2s, I2S_SOFT_RESET, I2S_SOFT_RESET_TX_BIT);
chv3_i2s_wr(i2s, I2S_TX_BASE_ADDR, substream->dma_buffer.addr);
chv3_i2s_wr(i2s, I2S_TX_BUFFER_SIZE, buffer_bytes);
chv3_i2s_wr(i2s, I2S_TX_IRQ, ((period_bytes / i2s->tx_bytes_to_fetch) << 8) | 1);
chv3_i2s_wr(i2s, I2S_TX_ENABLE, 1);
}
writel(I2S_IRQ_RX_BIT | I2S_IRQ_TX_BIT, i2s->iobase_irq + I2S_IRQ_MASK);
return 0;
}
static snd_pcm_uframes_t chv3_dma_pointer(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct chv3_i2s_dev *i2s = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
u32 frame_bytes, buffer_bytes;
u32 idx_bytes;
frame_bytes = substream->runtime->frame_bits * 8;
buffer_bytes = snd_pcm_lib_buffer_bytes(substream);
if (substream->pstr->stream == SNDRV_PCM_STREAM_CAPTURE) {
idx_bytes = chv3_i2s_rd(i2s, I2S_RX_PRODUCER_IDX);
} else {
idx_bytes = chv3_i2s_rd(i2s, I2S_TX_CONSUMER_IDX);
/* lag the pointer by one frame */
idx_bytes = (idx_bytes - frame_bytes) & (buffer_bytes - 1);
}
return bytes_to_frames(substream->runtime, idx_bytes);
}
static int chv3_dma_ack(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
struct snd_pcm_runtime *runtime = substream->runtime;
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct chv3_i2s_dev *i2s = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
unsigned int bytes, idx;
bytes = frames_to_bytes(runtime, runtime->control->appl_ptr);
idx = bytes & (snd_pcm_lib_buffer_bytes(substream) - 1);
if (substream->pstr->stream == SNDRV_PCM_STREAM_CAPTURE)
chv3_i2s_wr(i2s, I2S_RX_CONSUMER_IDX, idx);
else
chv3_i2s_wr(i2s, I2S_TX_PRODUCER_IDX, idx);
return 0;
}
static const struct snd_soc_component_driver chv3_i2s_comp = {
.name = "chv3-i2s-comp",
.open = chv3_dma_open,
.close = chv3_dma_close,
.pcm_construct = chv3_dma_pcm_construct,
.hw_params = chv3_dma_hw_params,
.prepare = chv3_dma_prepare,
.pointer = chv3_dma_pointer,
.ack = chv3_dma_ack,
};
static int chv3_i2s_probe(struct platform_device *pdev)
{
struct chv3_i2s_dev *i2s;
int res;
int irq;
i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL);
if (!i2s)
return -ENOMEM;
i2s->iobase = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(i2s->iobase))
return PTR_ERR(i2s->iobase);
i2s->iobase_irq = devm_platform_ioremap_resource(pdev, 1);
if (IS_ERR(i2s->iobase_irq))
return PTR_ERR(i2s->iobase_irq);
i2s->tx_bytes_to_fetch = (chv3_i2s_rd(i2s, I2S_TX_IRQ_CONST) >> 8) & 0xffff;
i2s->dev = &pdev->dev;
dev_set_drvdata(&pdev->dev, i2s);
irq = platform_get_irq(pdev, 0);
if (irq < 0)
return -ENXIO;
res = devm_request_irq(i2s->dev, irq, chv3_i2s_isr, 0, "chv3-i2s", i2s);
if (res)
return res;
res = devm_snd_soc_register_component(&pdev->dev, &chv3_i2s_comp,
&chv3_i2s_dai, 1);
if (res) {
dev_err(&pdev->dev, "couldn't register component: %d\n", res);
return res;
}
return 0;
}
static const struct of_device_id chv3_i2s_of_match[] = {
{ .compatible = "google,chv3-i2s" },
{},
};
static struct platform_driver chv3_i2s_driver = {
.probe = chv3_i2s_probe,
.driver = {
.name = "chv3-i2s",
.of_match_table = chv3_i2s_of_match,
},
};
module_platform_driver(chv3_i2s_driver);
MODULE_AUTHOR("Pawel Anikiel <pan@semihalf.com>");
MODULE_DESCRIPTION("Chameleon v3 I2S interface");
MODULE_LICENSE("GPL");