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ARM: s3c24xx: simplify mach/io.h
s3c24xx has a custom implementation of the inb/outb family of I/O accessors, implementing both general register access and ISA I/O port through a multiplexer. As far as I can tell, the first case has never been needed, and certainly is not used now, as drivers only use inb/outb to actually driver ISA or PCI port I/O. Similarly, the special ISA support is limited to a single machine, the Simtec Electronics BAST (EB2410ITX) with its PC/104 expansion connector, all other machines could simply use the generic implementation from asm/io.h that expects a single memory-mapped address range for byte, word and dword access. As no other machines besides BAST actually selects CONFIG_ISA, this is likely not even necessary. As a cleanup, remove support for the non-ISA access from the helpers, and make the ISA access use the virtual address window that we use elsewhere for PCI I/O ports. In configurations without the BAST machine, this now falls back on the generic implementation from asm/io.h, but the mach/io.h header is still relied on to include a number of other header files implicitly. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Link: https://lore.kernel.org/r/20200806182059.2431-7-krzk@kernel.org Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
This commit is contained in:
Arnd Bergmann
Krzysztof Kozlowski
parent
b84e23f513
commit
98c2922ec8
2 changed files with 27 additions and 194 deletions
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@ -12,201 +12,40 @@
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#include <mach/hardware.h>
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#define IO_SPACE_LIMIT 0xffffffff
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/*
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* We use two different types of addressing - PC style addresses, and ARM
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* addresses. PC style accesses the PC hardware with the normal PC IO
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* addresses, eg 0x3f8 for serial#1. ARM addresses are above A28
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* and are translated to the start of IO. Note that all addresses are
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* not shifted left!
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* ISA style IO, for each machine to sort out mappings for,
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* if it implements it. We reserve two 16M regions for ISA,
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* so the PC/104 can use separate addresses for 8-bit and
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* 16-bit port I/O.
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*/
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#define PCIO_BASE S3C_ADDR(0x02000000)
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#define IO_SPACE_LIMIT 0x00ffffff
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#define S3C24XX_VA_ISA_WORD (PCIO_BASE)
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#define S3C24XX_VA_ISA_BYTE (PCIO_BASE + 0x01000000)
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#define __PORT_PCIO(x) ((x) < (1<<28))
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#ifdef CONFIG_ISA
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#define PCIO_BASE (S3C24XX_VA_ISA_WORD)
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#define PCIO_BASE_b (S3C24XX_VA_ISA_BYTE)
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#define PCIO_BASE_w (S3C24XX_VA_ISA_WORD)
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#define PCIO_BASE_l (S3C24XX_VA_ISA_WORD)
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/*
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* Dynamic IO functions - let the compiler
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* optimize the expressions
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*/
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#define inb(p) readb(S3C24XX_VA_ISA_BYTE + (p))
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#define inw(p) readw(S3C24XX_VA_ISA_WORD + (p))
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#define inl(p) readl(S3C24XX_VA_ISA_WORD + (p))
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#define DECLARE_DYN_OUT(sz,fnsuffix,instr) \
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static inline void __out##fnsuffix (unsigned int val, unsigned int port) \
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{ \
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unsigned long temp; \
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__asm__ __volatile__( \
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"cmp %2, #(1<<28)\n\t" \
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"mov %0, %2\n\t" \
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"addcc %0, %0, %3\n\t" \
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"str" instr " %1, [%0, #0 ] @ out" #fnsuffix \
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: "=&r" (temp) \
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: "r" (val), "r" (port), "Ir" (PCIO_BASE_##fnsuffix) \
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: "cc"); \
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}
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#define outb(v,p) writeb((v), S3C24XX_VA_ISA_BYTE + (p))
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#define outw(v,p) writew((v), S3C24XX_VA_ISA_WORD + (p))
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#define outl(v,p) writel((v), S3C24XX_VA_ISA_WORD + (p))
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#define insb(p,d,l) readsb(S3C24XX_VA_ISA_BYTE + (p),d,l)
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#define insw(p,d,l) readsw(S3C24XX_VA_ISA_WORD + (p),d,l)
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#define insl(p,d,l) readsl(S3C24XX_VA_ISA_WORD + (p),d,l)
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#define DECLARE_DYN_IN(sz,fnsuffix,instr) \
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static inline unsigned sz __in##fnsuffix (unsigned int port) \
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{ \
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unsigned long temp, value; \
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__asm__ __volatile__( \
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"cmp %2, #(1<<28)\n\t" \
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"mov %0, %2\n\t" \
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"addcc %0, %0, %3\n\t" \
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"ldr" instr " %1, [%0, #0 ] @ in" #fnsuffix \
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: "=&r" (temp), "=r" (value) \
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: "r" (port), "Ir" (PCIO_BASE_##fnsuffix) \
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: "cc"); \
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return (unsigned sz)value; \
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}
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#define outsb(p,d,l) writesb(S3C24XX_VA_ISA_BYTE + (p),d,l)
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#define outsw(p,d,l) writesw(S3C24XX_VA_ISA_WORD + (p),d,l)
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#define outsl(p,d,l) writesl(S3C24XX_VA_ISA_WORD + (p),d,l)
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static inline void __iomem *__ioaddr (unsigned long port)
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{
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return __PORT_PCIO(port) ? (PCIO_BASE + port) : (void __iomem *)port;
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}
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#else
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#define DECLARE_IO(sz,fnsuffix,instr) \
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DECLARE_DYN_IN(sz,fnsuffix,instr) \
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DECLARE_DYN_OUT(sz,fnsuffix,instr)
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DECLARE_IO(char,b,"b")
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DECLARE_IO(short,w,"h")
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DECLARE_IO(int,l,"")
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#undef DECLARE_IO
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#undef DECLARE_DYN_IN
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/*
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* Constant address IO functions
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*
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* These have to be macros for the 'J' constraint to work -
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* +/-4096 immediate operand.
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*/
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#define __outbc(value,port) \
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({ \
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if (__PORT_PCIO((port))) \
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__asm__ __volatile__( \
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"strb %0, [%1, %2] @ outbc" \
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: : "r" (value), "r" (PCIO_BASE), "Jr" ((port))); \
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else \
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__asm__ __volatile__( \
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"strb %0, [%1, #0] @ outbc" \
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: : "r" (value), "r" ((port))); \
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})
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#define __inbc(port) \
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({ \
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unsigned char result; \
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if (__PORT_PCIO((port))) \
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__asm__ __volatile__( \
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"ldrb %0, [%1, %2] @ inbc" \
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: "=r" (result) : "r" (PCIO_BASE), "Jr" ((port))); \
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else \
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__asm__ __volatile__( \
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"ldrb %0, [%1, #0] @ inbc" \
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: "=r" (result) : "r" ((port))); \
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result; \
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})
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#define __outwc(value,port) \
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({ \
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unsigned long v = value; \
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if (__PORT_PCIO((port))) { \
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if ((port) < 256 && (port) > -256) \
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__asm__ __volatile__( \
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"strh %0, [%1, %2] @ outwc" \
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: : "r" (v), "r" (PCIO_BASE), "Jr" ((port))); \
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else if ((port) > 0) \
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__asm__ __volatile__( \
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"strh %0, [%1, %2] @ outwc" \
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: : "r" (v), \
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"r" (PCIO_BASE + ((port) & ~0xff)), \
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"Jr" (((port) & 0xff))); \
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else \
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__asm__ __volatile__( \
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"strh %0, [%1, #0] @ outwc" \
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: : "r" (v), \
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"r" (PCIO_BASE + (port))); \
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} else \
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__asm__ __volatile__( \
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"strh %0, [%1, #0] @ outwc" \
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: : "r" (v), "r" ((port))); \
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})
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#define __inwc(port) \
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({ \
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unsigned short result; \
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if (__PORT_PCIO((port))) { \
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if ((port) < 256 && (port) > -256 ) \
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__asm__ __volatile__( \
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"ldrh %0, [%1, %2] @ inwc" \
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: "=r" (result) \
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: "r" (PCIO_BASE), \
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"Jr" ((port))); \
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else if ((port) > 0) \
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__asm__ __volatile__( \
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"ldrh %0, [%1, %2] @ inwc" \
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: "=r" (result) \
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: "r" (PCIO_BASE + ((port) & ~0xff)), \
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"Jr" (((port) & 0xff))); \
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else \
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__asm__ __volatile__( \
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"ldrh %0, [%1, #0] @ inwc" \
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: "=r" (result) \
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: "r" (PCIO_BASE + ((port)))); \
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} else \
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__asm__ __volatile__( \
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"ldrh %0, [%1, #0] @ inwc" \
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: "=r" (result) : "r" ((port))); \
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result; \
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})
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#define __outlc(value,port) \
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({ \
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unsigned long v = value; \
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if (__PORT_PCIO((port))) \
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__asm__ __volatile__( \
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"str %0, [%1, %2] @ outlc" \
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: : "r" (v), "r" (PCIO_BASE), "Jr" ((port))); \
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else \
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__asm__ __volatile__( \
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"str %0, [%1, #0] @ outlc" \
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: : "r" (v), "r" ((port))); \
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})
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#define __inlc(port) \
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({ \
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unsigned long result; \
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if (__PORT_PCIO((port))) \
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__asm__ __volatile__( \
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"ldr %0, [%1, %2] @ inlc" \
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: "=r" (result) : "r" (PCIO_BASE), "Jr" ((port))); \
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else \
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__asm__ __volatile__( \
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"ldr %0, [%1, #0] @ inlc" \
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: "=r" (result) : "r" ((port))); \
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result; \
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})
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#define __ioaddrc(port) ((__PORT_PCIO(port) ? PCIO_BASE + (port) : (void __iomem *)0 + (port)))
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#define inb(p) (__builtin_constant_p((p)) ? __inbc(p) : __inb(p))
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#define inw(p) (__builtin_constant_p((p)) ? __inwc(p) : __inw(p))
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#define inl(p) (__builtin_constant_p((p)) ? __inlc(p) : __inl(p))
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#define outb(v,p) (__builtin_constant_p((p)) ? __outbc(v,p) : __outb(v,p))
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#define outw(v,p) (__builtin_constant_p((p)) ? __outwc(v,p) : __outw(v,p))
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#define outl(v,p) (__builtin_constant_p((p)) ? __outlc(v,p) : __outl(v,p))
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#define __ioaddr(p) (__builtin_constant_p((p)) ? __ioaddr(p) : __ioaddrc(p))
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#define insb(p,d,l) __raw_readsb(__ioaddr(p),d,l)
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#define insw(p,d,l) __raw_readsw(__ioaddr(p),d,l)
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#define insl(p,d,l) __raw_readsl(__ioaddr(p),d,l)
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#define outsb(p,d,l) __raw_writesb(__ioaddr(p),d,l)
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#define outsw(p,d,l) __raw_writesw(__ioaddr(p),d,l)
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#define outsl(p,d,l) __raw_writesl(__ioaddr(p),d,l)
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#define __io(x) (PCIO_BASE + (x))
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#endif
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#endif
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@ -9,6 +9,8 @@
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#ifndef __ASM_PLAT_MAP_S3C_H
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#define __ASM_PLAT_MAP_S3C_H __FILE__
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#include <mach/map.h>
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#define S3C24XX_VA_IRQ S3C_VA_IRQ
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#define S3C24XX_VA_MEMCTRL S3C_VA_MEM
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#define S3C24XX_VA_UART S3C_VA_UART
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@ -45,16 +47,8 @@
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#define S3C_VA_USB_HSPHY S3C64XX_VA_USB_HSPHY
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/*
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* ISA style IO, for each machine to sort out mappings for,
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* if it implements it. We reserve two 16M regions for ISA.
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*/
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#define S3C2410_ADDR(x) S3C_ADDR(x)
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#define S3C24XX_VA_ISA_WORD S3C2410_ADDR(0x02000000)
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#define S3C24XX_VA_ISA_BYTE S3C2410_ADDR(0x03000000)
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/* deal with the registers that move under the 2412/2413 */
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#if defined(CONFIG_CPU_S3C2412)
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