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ARM: tegra: acer-a500: Use PLLC for WiFi MMC clock parent

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The default parent for all MMCs is PLLP, which is running at 216 MHz on
Tegra20 and 50 MHz clock can't be derived from PLLP. The maximum SDIO
clock rate is 50 MHz, but this rate isn't achievable using PLLP.

Let's switch the WiFi MMC clock parent to PLLC in order to get true 50
MHz. This patch doesn't fix any problems, it's just a minor improvement.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
This commit is contained in:
Dmitry Osipenko 2020-08-23 17:47:24 +03:00 committed by Thierry Reding
parent a252efadf3
commit 98e710a017
1 changed files with 4 additions and 0 deletions
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4
arch/arm/boot/dts/tegra20-acer-a500-picasso.dts
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@ -736,6 +736,10 @@ sdmmc1: mmc@c8000000 {
#address-cells = <1>;
#size-cells = <0>;
assigned-clocks = <&tegra_car TEGRA20_CLK_SDMMC1>;
assigned-clock-parents = <&tegra_car TEGRA20_CLK_PLL_C>;
assigned-clock-rates = <50000000>;
max-frequency = <50000000>;
keep-power-in-suspend;
bus-width = <4>;