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synced 2024-09-06 02:50:43 +00:00
drm/msm/mdp5: Add MDSS top level driver
SoCs that contain MDP5 have a top level wrapper called MDSS that manages clocks, power and irq for the sub-blocks within it. Currently, the MDSS portions are stuffed into the MDP5 driver. This makes it hard to represent the DT bindings in the correct way. We create a top level MDSS helper that handles these parts. This is essentially moving out some of the mdp5_kms irq code and MDSS register space and keeping it as a separate entity. We haven't given any clocks to the top level MDSS yet, but a AHB clock would be added in the future to access registers. One thing to note is that the resources allocated by this helper are tied to the top level platform_device (the one that allocates the drm_device struct too). This device would be the parent to MDSS sub-blocks like MDP5, DSI, eDP etc. Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
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4 changed files with 230 additions and 0 deletions
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@ -35,6 +35,7 @@ msm-y := \
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mdp/mdp5/mdp5_crtc.o \
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mdp/mdp5/mdp5_encoder.o \
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mdp/mdp5/mdp5_irq.o \
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mdp/mdp5/mdp5_mdss.o \
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mdp/mdp5/mdp5_kms.o \
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mdp/mdp5/mdp5_plane.o \
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mdp/mdp5/mdp5_smp.o \
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223
drivers/gpu/drm/msm/mdp/mdp5/mdp5_mdss.c
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drivers/gpu/drm/msm/mdp/mdp5/mdp5_mdss.c
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@ -0,0 +1,223 @@
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/*
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* Copyright (c) 2016, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published by
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* the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/irqdomain.h>
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#include <linux/irq.h>
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#include "msm_drv.h"
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#include "mdp5_kms.h"
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/*
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* If needed, this can become more specific: something like struct mdp5_mdss,
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* which contains a 'struct msm_mdss base' member.
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*/
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struct msm_mdss {
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struct drm_device *dev;
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void __iomem *mmio, *vbif;
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struct regulator *vdd;
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struct {
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volatile unsigned long enabled_mask;
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struct irq_domain *domain;
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} irqcontroller;
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};
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static inline void mdss_write(struct msm_mdss *mdss, u32 reg, u32 data)
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{
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msm_writel(data, mdss->mmio + reg);
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}
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static inline u32 mdss_read(struct msm_mdss *mdss, u32 reg)
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{
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return msm_readl(mdss->mmio + reg);
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}
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static irqreturn_t mdss_irq(int irq, void *arg)
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{
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struct msm_mdss *mdss = arg;
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u32 intr;
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intr = mdss_read(mdss, REG_MDSS_HW_INTR_STATUS);
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VERB("intr=%08x", intr);
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while (intr) {
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irq_hw_number_t hwirq = fls(intr) - 1;
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generic_handle_irq(irq_find_mapping(
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mdss->irqcontroller.domain, hwirq));
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intr &= ~(1 << hwirq);
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}
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return IRQ_HANDLED;
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}
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/*
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* interrupt-controller implementation, so sub-blocks (MDP/HDMI/eDP/DSI/etc)
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* can register to get their irq's delivered
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*/
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#define VALID_IRQS (MDSS_HW_INTR_STATUS_INTR_MDP | \
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MDSS_HW_INTR_STATUS_INTR_DSI0 | \
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MDSS_HW_INTR_STATUS_INTR_DSI1 | \
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MDSS_HW_INTR_STATUS_INTR_HDMI | \
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MDSS_HW_INTR_STATUS_INTR_EDP)
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static void mdss_hw_mask_irq(struct irq_data *irqd)
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{
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struct msm_mdss *mdss = irq_data_get_irq_chip_data(irqd);
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smp_mb__before_atomic();
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clear_bit(irqd->hwirq, &mdss->irqcontroller.enabled_mask);
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smp_mb__after_atomic();
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}
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static void mdss_hw_unmask_irq(struct irq_data *irqd)
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{
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struct msm_mdss *mdss = irq_data_get_irq_chip_data(irqd);
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smp_mb__before_atomic();
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set_bit(irqd->hwirq, &mdss->irqcontroller.enabled_mask);
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smp_mb__after_atomic();
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}
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static struct irq_chip mdss_hw_irq_chip = {
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.name = "mdss",
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.irq_mask = mdss_hw_mask_irq,
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.irq_unmask = mdss_hw_unmask_irq,
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};
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static int mdss_hw_irqdomain_map(struct irq_domain *d, unsigned int irq,
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irq_hw_number_t hwirq)
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{
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struct msm_mdss *mdss = d->host_data;
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if (!(VALID_IRQS & (1 << hwirq)))
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return -EPERM;
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irq_set_chip_and_handler(irq, &mdss_hw_irq_chip, handle_level_irq);
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irq_set_chip_data(irq, mdss);
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return 0;
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}
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static struct irq_domain_ops mdss_hw_irqdomain_ops = {
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.map = mdss_hw_irqdomain_map,
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.xlate = irq_domain_xlate_onecell,
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};
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static int mdss_irq_domain_init(struct msm_mdss *mdss)
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{
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struct device *dev = mdss->dev->dev;
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struct irq_domain *d;
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d = irq_domain_add_linear(dev->of_node, 32, &mdss_hw_irqdomain_ops,
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mdss);
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if (!d) {
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dev_err(dev, "mdss irq domain add failed\n");
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return -ENXIO;
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}
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mdss->irqcontroller.enabled_mask = 0;
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mdss->irqcontroller.domain = d;
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return 0;
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}
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void msm_mdss_destroy(struct drm_device *dev)
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{
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struct msm_drm_private *priv = dev->dev_private;
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struct msm_mdss *mdss = priv->mdss;
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if (!mdss)
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return;
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irq_domain_remove(mdss->irqcontroller.domain);
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mdss->irqcontroller.domain = NULL;
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regulator_disable(mdss->vdd);
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}
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int msm_mdss_init(struct drm_device *dev)
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{
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struct platform_device *pdev = dev->platformdev;
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struct msm_drm_private *priv = dev->dev_private;
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struct msm_mdss *mdss;
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int ret;
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DBG("");
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if (!of_device_is_compatible(dev->dev->of_node, "qcom,mdss"))
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return 0;
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mdss = devm_kzalloc(dev->dev, sizeof(*mdss), GFP_KERNEL);
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if (!mdss) {
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ret = -ENOMEM;
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goto fail;
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}
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mdss->dev = dev;
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mdss->mmio = msm_ioremap(pdev, "mdss_phys", "MDSS");
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if (IS_ERR(mdss->mmio)) {
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ret = PTR_ERR(mdss->mmio);
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goto fail;
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}
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mdss->vbif = msm_ioremap(pdev, "vbif_phys", "VBIF");
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if (IS_ERR(mdss->vbif)) {
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ret = PTR_ERR(mdss->vbif);
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goto fail;
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}
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/* Regulator to enable GDSCs in downstream kernels */
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mdss->vdd = devm_regulator_get(dev->dev, "vdd");
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if (IS_ERR(mdss->vdd)) {
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ret = PTR_ERR(mdss->vdd);
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goto fail;
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}
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ret = regulator_enable(mdss->vdd);
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if (ret) {
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dev_err(dev->dev, "failed to enable regulator vdd: %d\n",
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ret);
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goto fail;
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}
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ret = devm_request_irq(dev->dev, platform_get_irq(pdev, 0),
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mdss_irq, 0, "mdss_isr", mdss);
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if (ret) {
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dev_err(dev->dev, "failed to init irq: %d\n", ret);
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goto fail_irq;
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}
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ret = mdss_irq_domain_init(mdss);
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if (ret) {
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dev_err(dev->dev, "failed to init sub-block irqs: %d\n", ret);
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goto fail_irq;
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}
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priv->mdss = mdss;
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return 0;
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fail_irq:
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regulator_disable(mdss->vdd);
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fail:
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return ret;
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}
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@ -46,6 +46,7 @@
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struct msm_kms;
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struct msm_gpu;
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struct msm_mmu;
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struct msm_mdss;
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struct msm_rd_state;
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struct msm_perf_state;
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struct msm_gem_submit;
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/* subordinate devices, if present: */
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struct platform_device *gpu_pdev;
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/* top level MDSS wrapper device (for MDP5 only) */
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struct msm_mdss *mdss;
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/* possibly this should be in the kms component, but it is
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* shared by both mdp4 and mdp5..
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*/
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@ -73,5 +73,7 @@ static inline void msm_kms_init(struct msm_kms *kms,
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struct msm_kms *mdp4_kms_init(struct drm_device *dev);
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struct msm_kms *mdp5_kms_init(struct drm_device *dev);
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int msm_mdss_init(struct drm_device *dev);
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void msm_mdss_destroy(struct drm_device *dev);
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#endif /* __MSM_KMS_H__ */
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