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drm/amd/powerplay: fix issue can't enable vce dpm.
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Eric Huang <JinhuiEric.Huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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parent
ec38f1889a
commit
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3 changed files with 22 additions and 28 deletions
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@ -131,11 +131,19 @@ int polaris10_phm_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate)
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data->vce_power_gated = bgate;
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if (bgate)
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if (bgate) {
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cgs_set_clockgating_state(hwmgr->device,
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AMD_IP_BLOCK_TYPE_VCE,
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AMD_CG_STATE_GATE);
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polaris10_update_vce_dpm(hwmgr, true);
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polaris10_phm_powerdown_vce(hwmgr);
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else
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} else {
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polaris10_phm_powerup_vce(hwmgr);
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polaris10_update_vce_dpm(hwmgr, false);
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cgs_set_clockgating_state(hwmgr->device,
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AMD_IP_BLOCK_TYPE_VCE,
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AMD_CG_STATE_UNGATE);
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}
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return 0;
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}
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@ -4424,25 +4424,20 @@ int polaris10_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate)
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return polaris10_enable_disable_uvd_dpm(hwmgr, !bgate);
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}
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static int polaris10_update_vce_dpm(struct pp_hwmgr *hwmgr, const void *input)
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int polaris10_update_vce_dpm(struct pp_hwmgr *hwmgr, bool bgate)
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{
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const struct phm_set_power_state_input *states =
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(const struct phm_set_power_state_input *)input;
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struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
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const struct polaris10_power_state *polaris10_nps =
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cast_const_phw_polaris10_power_state(states->pnew_state);
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const struct polaris10_power_state *polaris10_cps =
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cast_const_phw_polaris10_power_state(states->pcurrent_state);
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uint32_t mm_boot_level_offset, mm_boot_level_value;
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struct phm_ppt_v1_information *table_info =
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(struct phm_ppt_v1_information *)(hwmgr->pptable);
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if (polaris10_nps->vce_clks.evclk > 0 &&
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(polaris10_cps == NULL || polaris10_cps->vce_clks.evclk == 0)) {
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data->smc_state_table.VceBootLevel =
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if (!bgate) {
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if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
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PHM_PlatformCaps_StablePState))
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data->smc_state_table.VceBootLevel =
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(uint8_t) (table_info->mm_dep_table->count - 1);
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else
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data->smc_state_table.VceBootLevel = 0;
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mm_boot_level_offset = data->dpm_table_start +
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offsetof(SMU74_Discrete_DpmTable, VceBootLevel);
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@ -4455,18 +4450,14 @@ static int polaris10_update_vce_dpm(struct pp_hwmgr *hwmgr, const void *input)
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cgs_write_ind_register(hwmgr->device,
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CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
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if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState)) {
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if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState))
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smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
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PPSMC_MSG_VCEDPM_SetEnabledMask,
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(uint32_t)1 << data->smc_state_table.VceBootLevel);
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polaris10_enable_disable_vce_dpm(hwmgr, true);
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} else if (polaris10_nps->vce_clks.evclk == 0 &&
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polaris10_cps != NULL &&
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polaris10_cps->vce_clks.evclk > 0)
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polaris10_enable_disable_vce_dpm(hwmgr, false);
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}
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polaris10_enable_disable_vce_dpm(hwmgr, !bgate);
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return 0;
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}
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@ -4655,11 +4646,6 @@ static int polaris10_set_power_state_tasks(struct pp_hwmgr *hwmgr, const void *i
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"Failed to generate DPM level enabled mask!",
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result = tmp_result);
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tmp_result = polaris10_update_vce_dpm(hwmgr, input);
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PP_ASSERT_WITH_CODE((0 == tmp_result),
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"Failed to update VCE DPM!",
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result = tmp_result);
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tmp_result = polaris10_update_sclk_threshold(hwmgr);
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PP_ASSERT_WITH_CODE((0 == tmp_result),
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"Failed to update SCLK threshold!",
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@ -352,6 +352,6 @@ int polaris10_hwmgr_init(struct pp_hwmgr *hwmgr);
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int polaris10_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate);
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int polaris10_update_samu_dpm(struct pp_hwmgr *hwmgr, bool bgate);
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int polaris10_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable);
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int polaris10_update_vce_dpm(struct pp_hwmgr *hwmgr, bool bgate);
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#endif
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