mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-09-06 02:50:43 +00:00
The Freescale/NXP arm64 device tree updates for 4.7:
- New board support of LS1043a-QDS from Freescale/NXP - Add new compatible for LS1043A and LS2080A GPIO devices - Update device tree bindings and sources for LS2080A fsl-mc device - Update QSPI and DSPI support on LS1043A and LS2080A -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQEcBAABAgAGBQJXKL1RAAoJEFBXWFqHsHzOdO8H/1HeVve6KqhjpgHEYI0vqCQN F8dC3kA8S9UZcozl58VrKvH+ArR2dcumfdl6ov/WVdfuWDwcBN3SKYgCK4xV1aN9 QtxFkc7uiE4InyDl4w9Q3fGRZfCgzk3eYUWQmHw6D0oQc3UhoIZ3cK+aKMB2nlZ1 Q4e0pO3Ell96sKYIhaG6rltlLc9U6Ax4z1XDl1CZ/T2njARFqwBfgNkjSdguB0Ks +GOCd/TyloncdWoC41MQnwaOWc+msa3rkXJG2Aj1PWyocZPIiY0K68RClv1g/yKk XZJ3M574QK+n/+Em0t+QaxrggiqT6kzr00CfULyyXQ4xhZO1siByCuxdEFW/tAs= =pZW5 -----END PGP SIGNATURE----- Merge tag 'imx-dt64-4.7' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/dt64 Merge "The Freescale/NXP arm64 device tree updates for 4.7" from Shawn Guo: - New board support of LS1043a-QDS from Freescale/NXP - Add new compatible for LS1043A and LS2080A GPIO devices - Update device tree bindings and sources for LS2080A fsl-mc device - Update QSPI and DSPI support on LS1043A and LS2080A * tag 'imx-dt64-4.7' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: arm64: dts: ls2080a: fsl-mc dt node updates Documentation: fsl-mc: binding updates for MSIs, ranges, PHYs arm64: dts: ls1043a: add the DTS node for QSPI support Documentation: fsl-quadspi: Add fsl,ls1043a-qspi compatible string arm64: dts: ls2080a: Add compatible "fsl,ls2080a-gpio" for ls2080a gpio nodes arm64: dts: ls1043a: Add compatible "fsl,qoriq-gpio" for ls1043a gpio nodes arm64: dts: ls2080a: update the DTS for QSPI and DSPI support Documentation: fsl: dspi: Add fsl,ls2080a-dspi compatible string arm64: dts: ls1043a-rdb: add the DTS for DSPI support arm64: dts: add LS1043a-QDS board support Documentation: DT: Add entry for Freescale LS1043a-QDS board
This commit is contained in:
commit
9910f5b199
10 changed files with 416 additions and 15 deletions
|
@ -135,6 +135,10 @@ LS1043A ARMv8 based RDB Board
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|||
Required root node properties:
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- compatible = "fsl,ls1043a-rdb", "fsl,ls1043a";
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LS1043A ARMv8 based QDS Board
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Required root node properties:
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- compatible = "fsl,ls1043a-qds", "fsl,ls1043a";
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LS2080A ARMv8 based Simulator model
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Required root node properties:
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- compatible = "fsl,ls2080a-simu", "fsl,ls2080a";
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@ -30,11 +30,90 @@ Required properties:
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region may not be present in some scenarios, such
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as in the device tree presented to a virtual machine.
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- msi-parent
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Value type: <phandle>
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Definition: Must be present and point to the MSI controller node
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handling message interrupts for the MC.
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- ranges
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Value type: <prop-encoded-array>
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Definition: A standard property. Defines the mapping between the child
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MC address space and the parent system address space.
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The MC address space is defined by 3 components:
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<region type> <offset hi> <offset lo>
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Valid values for region type are
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0x0 - MC portals
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0x1 - QBMAN portals
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- #address-cells
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Value type: <u32>
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Definition: Must be 3. (see definition in 'ranges' property)
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- #size-cells
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Value type: <u32>
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Definition: Must be 1.
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Sub-nodes:
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The fsl-mc node may optionally have dpmac sub-nodes that describe
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the relationship between the Ethernet MACs which belong to the MC
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and the Ethernet PHYs on the system board.
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The dpmac nodes must be under a node named "dpmacs" which contains
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the following properties:
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- #address-cells
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Value type: <u32>
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Definition: Must be present if dpmac sub-nodes are defined and must
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have a value of 1.
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- #size-cells
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Value type: <u32>
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Definition: Must be present if dpmac sub-nodes are defined and must
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have a value of 0.
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These nodes must have the following properties:
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- compatible
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Value type: <string>
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Definition: Must be "fsl,qoriq-mc-dpmac".
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- reg
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Value type: <prop-encoded-array>
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Definition: Specifies the id of the dpmac.
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- phy-handle
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Value type: <phandle>
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Definition: Specifies the phandle to the PHY device node associated
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with the this dpmac.
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Example:
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fsl_mc: fsl-mc@80c000000 {
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compatible = "fsl,qoriq-mc";
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reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
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<0x00000000 0x08340000 0 0x40000>; /* MC control reg */
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};
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msi-parent = <&its>;
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#address-cells = <3>;
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#size-cells = <1>;
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/*
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* Region type 0x0 - MC portals
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* Region type 0x1 - QBMAN portals
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*/
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ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
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0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
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dpmacs {
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#address-cells = <1>;
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#size-cells = <0>;
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dpmac@1 {
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compatible = "fsl,qoriq-mc-dpmac";
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reg = <1>;
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phy-handle = <&mdio0_phy0>;
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}
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}
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};
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@ -5,7 +5,8 @@ Required properties:
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"fsl,imx7d-qspi", "fsl,imx6ul-qspi",
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"fsl,ls1021a-qspi"
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or
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"fsl,ls2080a-qspi" followed by "fsl,ls1021a-qspi"
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"fsl,ls2080a-qspi" followed by "fsl,ls1021a-qspi",
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"fsl,ls1043a-qspi" followed by "fsl,ls1021a-qspi"
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- reg : the first contains the register location and length,
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the second contains the memory mapping address and length
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- reg-names: Should contain the reg names "QuadSPI" and "QuadSPI-memory"
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@ -1,7 +1,10 @@
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ARM Freescale DSPI controller
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Required properties:
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- compatible : "fsl,vf610-dspi", "fsl,ls1021a-v1.0-dspi", "fsl,ls2085a-dspi"
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- compatible : "fsl,vf610-dspi", "fsl,ls1021a-v1.0-dspi",
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"fsl,ls2085a-dspi"
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or
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"fsl,ls2080a-dspi" followed by "fsl,ls2085a-dspi"
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- reg : Offset and length of the register set for the device
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- interrupts : Should contain SPI controller interrupt
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- clocks: from common clock binding: handle to dspi clock.
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@ -1,7 +1,8 @@
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dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-qds.dtb
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dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-rdb.dtb
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dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-qds.dtb
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dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-rdb.dtb
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dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-simu.dtb
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dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-rdb.dtb
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always := $(dtb-y)
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subdir-y := $(dts-dirs)
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181
arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts
Normal file
181
arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts
Normal file
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@ -0,0 +1,181 @@
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/*
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* Device Tree Include file for Freescale Layerscape-1043A family SoC.
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*
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* Copyright 2014-2015, Freescale Semiconductor
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*
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* Mingkai Hu <Mingkai.hu@freescale.com>
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPLv2 or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Or, alternatively,
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use,
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
|
||||
* conditions:
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*
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||||
* The above copyright notice and this permission notice shall be
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||||
* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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/dts-v1/;
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/include/ "fsl-ls1043a.dtsi"
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/ {
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model = "LS1043A QDS Board";
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compatible = "fsl,ls1043a-qds", "fsl,ls1043a";
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aliases {
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gpio0 = &gpio1;
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gpio1 = &gpio2;
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gpio2 = &gpio3;
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gpio3 = &gpio4;
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serial0 = &lpuart0;
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serial1 = &lpuart1;
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serial2 = &lpuart2;
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serial3 = &lpuart3;
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serial4 = &lpuart4;
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serial5 = &lpuart5;
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};
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};
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&duart0 {
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status = "okay";
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};
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&duart1 {
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status = "okay";
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};
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&ifc {
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#address-cells = <2>;
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#size-cells = <1>;
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/* NOR, NAND Flashes and FPGA on board */
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ranges = <0x0 0x0 0x0 0x60000000 0x08000000
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0x1 0x0 0x0 0x7e800000 0x00010000
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0x2 0x0 0x0 0x7fb00000 0x00000100>;
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status = "okay";
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nor@0,0 {
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compatible = "cfi-flash";
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reg = <0x0 0x0 0x8000000>;
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bank-width = <2>;
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device-width = <1>;
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};
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nand@1,0 {
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compatible = "fsl,ifc-nand";
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reg = <0x1 0x0 0x10000>;
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};
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fpga: board-control@2,0 {
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compatible = "fsl,ls1043aqds-fpga", "fsl,fpga-qixis";
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reg = <0x2 0x0 0x0000100>;
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};
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};
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&i2c0 {
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status = "okay";
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pca9547@77 {
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compatible = "nxp,pca9547";
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reg = <0x77>;
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#address-cells = <1>;
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#size-cells = <0>;
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i2c@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0>;
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rtc@68 {
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compatible = "dallas,ds3232";
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reg = <0x68>;
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/* IRQ10_B */
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interrupts = <0 150 0x4>;
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};
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};
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i2c@2 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x2>;
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ina220@40 {
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compatible = "ti,ina220";
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reg = <0x40>;
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shunt-resistor = <1000>;
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};
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ina220@41 {
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compatible = "ti,ina220";
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reg = <0x41>;
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shunt-resistor = <1000>;
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};
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};
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i2c@3 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x3>;
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eeprom@56 {
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compatible = "atmel,24c512";
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reg = <0x56>;
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};
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eeprom@57 {
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compatible = "atmel,24c512";
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reg = <0x57>;
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};
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temp-sensor@4c {
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compatible = "adi,adt7461a";
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reg = <0x4c>;
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};
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};
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};
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};
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&lpuart0 {
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status = "okay";
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};
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&qspi {
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bus-num = <0>;
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status = "okay";
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qflash0: s25fl128s@0 {
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compatible = "spansion,m25p80";
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#address-cells = <1>;
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#size-cells = <1>;
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spi-max-frequency = <20000000>;
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reg = <0>;
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};
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};
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@ -107,6 +107,19 @@ cpld: board-control@2,0 {
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};
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};
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&dspi0 {
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bus-num = <0>;
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status = "okay";
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flash@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "n25q128a13", "jedec,spi-nor"; /* 16MB */
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reg = <0>;
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spi-max-frequency = <1000000>; /* input clock */
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};
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};
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&duart0 {
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status = "okay";
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};
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|
|
|
@ -171,6 +171,20 @@ ifc: ifc@1530000 {
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interrupts = <0 43 0x4>;
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};
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qspi: quadspi@1550000 {
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compatible = "fsl,ls1043a-qspi", "fsl,ls1021a-qspi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0 0x1550000 0x0 0x10000>,
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<0x0 0x40000000 0x0 0x4000000>;
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reg-names = "QuadSPI", "QuadSPI-memory";
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interrupts = <0 99 0x4>;
|
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clock-names = "qspi_en", "qspi";
|
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clocks = <&clockgen 4 0>, <&clockgen 4 0>;
|
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big-endian;
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status = "disabled";
|
||||
};
|
||||
|
||||
esdhc: esdhc@1560000 {
|
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compatible = "fsl,ls1043a-esdhc", "fsl,esdhc";
|
||||
reg = <0x0 0x1560000 0x0 0x10000>;
|
||||
|
@ -284,7 +298,7 @@ duart3: serial@21d0600 {
|
|||
};
|
||||
|
||||
gpio1: gpio@2300000 {
|
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compatible = "fsl,ls1043a-gpio";
|
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compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
|
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reg = <0x0 0x2300000 0x0 0x10000>;
|
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interrupts = <0 66 0x4>;
|
||||
gpio-controller;
|
||||
|
@ -294,7 +308,7 @@ gpio1: gpio@2300000 {
|
|||
};
|
||||
|
||||
gpio2: gpio@2310000 {
|
||||
compatible = "fsl,ls1043a-gpio";
|
||||
compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
|
||||
reg = <0x0 0x2310000 0x0 0x10000>;
|
||||
interrupts = <0 67 0x4>;
|
||||
gpio-controller;
|
||||
|
@ -304,7 +318,7 @@ gpio2: gpio@2310000 {
|
|||
};
|
||||
|
||||
gpio3: gpio@2320000 {
|
||||
compatible = "fsl,ls1043a-gpio";
|
||||
compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
|
||||
reg = <0x0 0x2320000 0x0 0x10000>;
|
||||
interrupts = <0 68 0x4>;
|
||||
gpio-controller;
|
||||
|
@ -314,7 +328,7 @@ gpio3: gpio@2320000 {
|
|||
};
|
||||
|
||||
gpio4: gpio@2330000 {
|
||||
compatible = "fsl,ls1043a-gpio";
|
||||
compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
|
||||
reg = <0x0 0x2330000 0x0 0x10000>;
|
||||
interrupts = <0 134 0x4>;
|
||||
gpio-controller;
|
||||
|
|
|
@ -178,7 +178,14 @@ dflash2: en25s64 {
|
|||
|
||||
&qspi {
|
||||
status = "okay";
|
||||
qflash0: s25fl008k {
|
||||
flash0: s25fl256s1@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "st,m25p80";
|
||||
spi-max-frequency = <20000000>;
|
||||
reg = <0>;
|
||||
};
|
||||
flash2: s25fl256s1@2 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "st,m25p80";
|
||||
|
|
|
@ -265,6 +265,104 @@ fsl_mc: fsl-mc@80c000000 {
|
|||
compatible = "fsl,qoriq-mc";
|
||||
reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
|
||||
<0x00000000 0x08340000 0 0x40000>; /* MC control reg */
|
||||
msi-parent = <&its>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <1>;
|
||||
|
||||
/*
|
||||
* Region type 0x0 - MC portals
|
||||
* Region type 0x1 - QBMAN portals
|
||||
*/
|
||||
ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
|
||||
0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
|
||||
|
||||
/*
|
||||
* Define the maximum number of MACs present on the SoC.
|
||||
*/
|
||||
dpmacs {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
dpmac1: dpmac@1 {
|
||||
compatible = "fsl,qoriq-mc-dpmac";
|
||||
reg = <0x1>;
|
||||
};
|
||||
|
||||
dpmac2: dpmac@2 {
|
||||
compatible = "fsl,qoriq-mc-dpmac";
|
||||
reg = <0x2>;
|
||||
};
|
||||
|
||||
dpmac3: dpmac@3 {
|
||||
compatible = "fsl,qoriq-mc-dpmac";
|
||||
reg = <0x3>;
|
||||
};
|
||||
|
||||
dpmac4: dpmac@4 {
|
||||
compatible = "fsl,qoriq-mc-dpmac";
|
||||
reg = <0x4>;
|
||||
};
|
||||
|
||||
dpmac5: dpmac@5 {
|
||||
compatible = "fsl,qoriq-mc-dpmac";
|
||||
reg = <0x5>;
|
||||
};
|
||||
|
||||
dpmac6: dpmac@6 {
|
||||
compatible = "fsl,qoriq-mc-dpmac";
|
||||
reg = <0x6>;
|
||||
};
|
||||
|
||||
dpmac7: dpmac@7 {
|
||||
compatible = "fsl,qoriq-mc-dpmac";
|
||||
reg = <0x7>;
|
||||
};
|
||||
|
||||
dpmac8: dpmac@8 {
|
||||
compatible = "fsl,qoriq-mc-dpmac";
|
||||
reg = <0x8>;
|
||||
};
|
||||
|
||||
dpmac9: dpmac@9 {
|
||||
compatible = "fsl,qoriq-mc-dpmac";
|
||||
reg = <0x9>;
|
||||
};
|
||||
|
||||
dpmac10: dpmac@a {
|
||||
compatible = "fsl,qoriq-mc-dpmac";
|
||||
reg = <0xa>;
|
||||
};
|
||||
|
||||
dpmac11: dpmac@b {
|
||||
compatible = "fsl,qoriq-mc-dpmac";
|
||||
reg = <0xb>;
|
||||
};
|
||||
|
||||
dpmac12: dpmac@c {
|
||||
compatible = "fsl,qoriq-mc-dpmac";
|
||||
reg = <0xc>;
|
||||
};
|
||||
|
||||
dpmac13: dpmac@d {
|
||||
compatible = "fsl,qoriq-mc-dpmac";
|
||||
reg = <0xd>;
|
||||
};
|
||||
|
||||
dpmac14: dpmac@e {
|
||||
compatible = "fsl,qoriq-mc-dpmac";
|
||||
reg = <0xe>;
|
||||
};
|
||||
|
||||
dpmac15: dpmac@f {
|
||||
compatible = "fsl,qoriq-mc-dpmac";
|
||||
reg = <0xf>;
|
||||
};
|
||||
|
||||
dpmac16: dpmac@10 {
|
||||
compatible = "fsl,qoriq-mc-dpmac";
|
||||
reg = <0x10>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
smmu: iommu@5000000 {
|
||||
|
@ -318,7 +416,7 @@ smmu: iommu@5000000 {
|
|||
|
||||
dspi: dspi@2100000 {
|
||||
status = "disabled";
|
||||
compatible = "fsl,vf610-dspi";
|
||||
compatible = "fsl,ls2080a-dspi", "fsl,ls2085a-dspi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x0 0x2100000 0x0 0x10000>;
|
||||
|
@ -342,7 +440,7 @@ esdhc: esdhc@2140000 {
|
|||
};
|
||||
|
||||
gpio0: gpio@2300000 {
|
||||
compatible = "fsl,qoriq-gpio";
|
||||
compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
|
||||
reg = <0x0 0x2300000 0x0 0x10000>;
|
||||
interrupts = <0 36 0x4>; /* Level high type */
|
||||
gpio-controller;
|
||||
|
@ -353,7 +451,7 @@ gpio0: gpio@2300000 {
|
|||
};
|
||||
|
||||
gpio1: gpio@2310000 {
|
||||
compatible = "fsl,qoriq-gpio";
|
||||
compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
|
||||
reg = <0x0 0x2310000 0x0 0x10000>;
|
||||
interrupts = <0 36 0x4>; /* Level high type */
|
||||
gpio-controller;
|
||||
|
@ -364,7 +462,7 @@ gpio1: gpio@2310000 {
|
|||
};
|
||||
|
||||
gpio2: gpio@2320000 {
|
||||
compatible = "fsl,qoriq-gpio";
|
||||
compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
|
||||
reg = <0x0 0x2320000 0x0 0x10000>;
|
||||
interrupts = <0 37 0x4>; /* Level high type */
|
||||
gpio-controller;
|
||||
|
@ -375,7 +473,7 @@ gpio2: gpio@2320000 {
|
|||
};
|
||||
|
||||
gpio3: gpio@2330000 {
|
||||
compatible = "fsl,qoriq-gpio";
|
||||
compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
|
||||
reg = <0x0 0x2330000 0x0 0x10000>;
|
||||
interrupts = <0 37 0x4>; /* Level high type */
|
||||
gpio-controller;
|
||||
|
@ -444,7 +542,7 @@ ifc: ifc@2240000 {
|
|||
|
||||
qspi: quadspi@20c0000 {
|
||||
status = "disabled";
|
||||
compatible = "fsl,vf610-qspi";
|
||||
compatible = "fsl,ls2080a-qspi", "fsl,ls1021a-qspi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x0 0x20c0000 0x0 0x10000>,
|
||||
|
|
Loading…
Reference in a new issue