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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
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Merge branch 'dpll-phase-offset-phase-adjust'
Arkadiusz Kubalewski says: ==================== dpll: add phase-offset and phase-adjust Improve monitoring and control over dpll devices. Allow user to receive measurement of phase difference between signals on pin and dpll (phase-offset). Allow user to receive and control adjustable value of pin's signal phase (phase-adjust). v4->v5: - rebase series on top of net-next/main, fix conflict - remove redundant attribute type definition in subset definition v3->v4: - do not increase do version of uAPI header as it is not needed (v3 did not have this change) - fix spelling around commit messages, argument descriptions and docs - add missing extack errors on failure set callbacks for pin phase adjust and frequency - remove ice check if value is already set, now redundant as checked in the dpll subsystem v2->v3: - do not increase do version of uAPI header as it is not needed v1->v2: - improve handling for error case of requesting the phase adjust set - align handling for error case of frequency set request with the approach introduced for phase adjust ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
commit
99620ea033
9 changed files with 517 additions and 18 deletions
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@ -173,6 +173,47 @@ in order to configure active input of a MUX-type pin, the user needs to
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request desired pin state of the child pin on the parent pin,
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as described in the ``MUX-type pins`` chapter.
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Phase offset measurement and adjustment
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========================================
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Device may provide ability to measure a phase difference between signals
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on a pin and its parent dpll device. If pin-dpll phase offset measurement
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is supported, it shall be provided with ``DPLL_A_PIN_PHASE_OFFSET``
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attribute for each parent dpll device.
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Device may also provide ability to adjust a signal phase on a pin.
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If pin phase adjustment is supported, minimal and maximal values that pin
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handle shall be provide to the user on ``DPLL_CMD_PIN_GET`` respond
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with ``DPLL_A_PIN_PHASE_ADJUST_MIN`` and ``DPLL_A_PIN_PHASE_ADJUST_MAX``
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attributes. Configured phase adjust value is provided with
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``DPLL_A_PIN_PHASE_ADJUST`` attribute of a pin, and value change can be
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requested with the same attribute with ``DPLL_CMD_PIN_SET`` command.
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=============================== ======================================
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``DPLL_A_PIN_ID`` configured pin id
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``DPLL_A_PIN_PHASE_ADJUST_MIN`` attr minimum value of phase adjustment
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``DPLL_A_PIN_PHASE_ADJUST_MAX`` attr maximum value of phase adjustment
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``DPLL_A_PIN_PHASE_ADJUST`` attr configured value of phase
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adjustment on parent dpll device
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``DPLL_A_PIN_PARENT_DEVICE`` nested attribute for requesting
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configuration on given parent dpll
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device
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``DPLL_A_PIN_PARENT_ID`` parent dpll device id
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``DPLL_A_PIN_PHASE_OFFSET`` attr measured phase difference
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between a pin and parent dpll device
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=============================== ======================================
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All phase related values are provided in pico seconds, which represents
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time difference between signals phase. The negative value means that
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phase of signal on pin is earlier in time than dpll's signal. Positive
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value means that phase of signal on pin is later in time than signal of
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a dpll.
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Phase adjust (also min and max) values are integers, but measured phase
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offset values are fractional with 3-digit decimal places and shell be
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divided with ``DPLL_PIN_PHASE_OFFSET_DIVIDER`` to get integer part and
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modulo divided to get fractional part.
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Configuration commands group
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============================
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@ -263,6 +304,12 @@ according to attribute purpose.
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frequencies
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``DPLL_A_PIN_ANY_FREQUENCY_MIN`` attr minimum value of frequency
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``DPLL_A_PIN_ANY_FREQUENCY_MAX`` attr maximum value of frequency
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``DPLL_A_PIN_PHASE_ADJUST_MIN`` attr minimum value of phase
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adjustment
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``DPLL_A_PIN_PHASE_ADJUST_MAX`` attr maximum value of phase
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adjustment
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``DPLL_A_PIN_PHASE_ADJUST`` attr configured value of phase
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adjustment on parent device
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``DPLL_A_PIN_PARENT_DEVICE`` nested attr for each parent device
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the pin is connected with
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``DPLL_A_PIN_PARENT_ID`` attr parent dpll device id
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@ -270,8 +317,10 @@ according to attribute purpose.
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dpll device
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``DPLL_A_PIN_STATE`` attr state of pin on the parent
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dpll device
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``DPLL_A_PIN_DIRECTION`` attr direction of a pin on the
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``DPLL_A_PIN_DIRECTION`` attr direction of a pin on the
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parent dpll device
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``DPLL_A_PIN_PHASE_OFFSET`` attr measured phase difference
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between a pin and parent dpll
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``DPLL_A_PIN_PARENT_PIN`` nested attr for each parent pin
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the pin is connected with
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``DPLL_A_PIN_PARENT_ID`` attr parent pin id
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@ -284,6 +333,8 @@ according to attribute purpose.
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``DPLL_CMD_PIN_SET`` command to set pins configuration
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``DPLL_A_PIN_ID`` attr unique a pin ID
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``DPLL_A_PIN_FREQUENCY`` attr requested frequency of a pin
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``DPLL_A_PIN_PHASE_ADJUST`` attr requested value of phase
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adjustment on parent device
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``DPLL_A_PIN_PARENT_DEVICE`` nested attr for each parent dpll
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device configuration request
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``DPLL_A_PIN_PARENT_ID`` attr parent dpll device id
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@ -164,6 +164,18 @@ definitions:
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-
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name: state-can-change
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doc: pin state can be changed
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-
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type: const
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name: phase-offset-divider
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value: 1000
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doc: |
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phase offset divider allows userspace to calculate a value of
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measured signal phase difference between a pin and dpll device
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as a fractional value with three digit decimal precision.
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Value of (DPLL_A_PHASE_OFFSET / DPLL_PHASE_OFFSET_DIVIDER) is an
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integer part of a measured phase offset value.
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Value of (DPLL_A_PHASE_OFFSET % DPLL_PHASE_OFFSET_DIVIDER) is a
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fractional part of a measured phase offset value.
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attribute-sets:
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-
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@ -272,6 +284,18 @@ attribute-sets:
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type: nest
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multi-attr: true
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nested-attributes: pin-parent-pin
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-
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name: phase-adjust-min
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type: s32
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-
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name: phase-adjust-max
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type: s32
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-
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name: phase-adjust
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type: s32
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-
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name: phase-offset
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type: s64
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-
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name: pin-parent-device
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subset-of: pin
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@ -284,6 +308,8 @@ attribute-sets:
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name: prio
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-
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name: state
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-
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name: phase-offset
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-
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name: pin-parent-pin
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subset-of: pin
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@ -431,6 +457,9 @@ operations:
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- capabilities
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- parent-device
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- parent-pin
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- phase-adjust-min
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- phase-adjust-max
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- phase-adjust
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dump:
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pre: dpll-lock-dumpit
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@ -458,6 +487,7 @@ operations:
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- state
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- parent-device
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- parent-pin
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- phase-adjust
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-
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name: pin-create-ntf
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doc: Notification about pin appearing
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|
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@ -212,6 +212,53 @@ dpll_msg_add_pin_direction(struct sk_buff *msg, struct dpll_pin *pin,
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return 0;
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}
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static int
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dpll_msg_add_pin_phase_adjust(struct sk_buff *msg, struct dpll_pin *pin,
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struct dpll_pin_ref *ref,
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struct netlink_ext_ack *extack)
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{
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const struct dpll_pin_ops *ops = dpll_pin_ops(ref);
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struct dpll_device *dpll = ref->dpll;
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s32 phase_adjust;
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int ret;
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if (!ops->phase_adjust_get)
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return 0;
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ret = ops->phase_adjust_get(pin, dpll_pin_on_dpll_priv(dpll, pin),
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dpll, dpll_priv(dpll),
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&phase_adjust, extack);
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if (ret)
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return ret;
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if (nla_put_s32(msg, DPLL_A_PIN_PHASE_ADJUST, phase_adjust))
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return -EMSGSIZE;
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return 0;
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}
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static int
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dpll_msg_add_phase_offset(struct sk_buff *msg, struct dpll_pin *pin,
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struct dpll_pin_ref *ref,
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struct netlink_ext_ack *extack)
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{
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const struct dpll_pin_ops *ops = dpll_pin_ops(ref);
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struct dpll_device *dpll = ref->dpll;
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s64 phase_offset;
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int ret;
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if (!ops->phase_offset_get)
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return 0;
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ret = ops->phase_offset_get(pin, dpll_pin_on_dpll_priv(dpll, pin),
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dpll, dpll_priv(dpll), &phase_offset,
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extack);
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if (ret)
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return ret;
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if (nla_put_64bit(msg, DPLL_A_PIN_PHASE_OFFSET, sizeof(phase_offset),
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&phase_offset, DPLL_A_PIN_PAD))
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return -EMSGSIZE;
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return 0;
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}
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static int
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dpll_msg_add_pin_freq(struct sk_buff *msg, struct dpll_pin *pin,
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struct dpll_pin_ref *ref, struct netlink_ext_ack *extack)
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@ -330,6 +377,9 @@ dpll_msg_add_pin_dplls(struct sk_buff *msg, struct dpll_pin *pin,
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if (ret)
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goto nest_cancel;
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ret = dpll_msg_add_pin_direction(msg, pin, ref, extack);
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if (ret)
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goto nest_cancel;
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ret = dpll_msg_add_phase_offset(msg, pin, ref, extack);
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if (ret)
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goto nest_cancel;
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nla_nest_end(msg, attr);
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@ -377,6 +427,15 @@ dpll_cmd_pin_get_one(struct sk_buff *msg, struct dpll_pin *pin,
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if (nla_put_u32(msg, DPLL_A_PIN_CAPABILITIES, prop->capabilities))
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return -EMSGSIZE;
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ret = dpll_msg_add_pin_freq(msg, pin, ref, extack);
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if (ret)
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return ret;
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if (nla_put_s32(msg, DPLL_A_PIN_PHASE_ADJUST_MIN,
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prop->phase_range.min))
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return -EMSGSIZE;
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if (nla_put_s32(msg, DPLL_A_PIN_PHASE_ADJUST_MAX,
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prop->phase_range.max))
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return -EMSGSIZE;
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ret = dpll_msg_add_pin_phase_adjust(msg, pin, ref, extack);
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if (ret)
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return ret;
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if (xa_empty(&pin->parent_refs))
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@ -416,7 +475,7 @@ dpll_device_get_one(struct dpll_device *dpll, struct sk_buff *msg,
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if (nla_put_u32(msg, DPLL_A_TYPE, dpll->type))
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return -EMSGSIZE;
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return ret;
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return 0;
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}
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static int
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@ -556,8 +615,10 @@ static int
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dpll_pin_freq_set(struct dpll_pin *pin, struct nlattr *a,
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struct netlink_ext_ack *extack)
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{
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u64 freq = nla_get_u64(a);
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struct dpll_pin_ref *ref;
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u64 freq = nla_get_u64(a), old_freq;
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struct dpll_pin_ref *ref, *failed;
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const struct dpll_pin_ops *ops;
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struct dpll_device *dpll;
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unsigned long i;
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int ret;
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|
@ -567,19 +628,51 @@ dpll_pin_freq_set(struct dpll_pin *pin, struct nlattr *a,
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}
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xa_for_each(&pin->dpll_refs, i, ref) {
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const struct dpll_pin_ops *ops = dpll_pin_ops(ref);
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struct dpll_device *dpll = ref->dpll;
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if (!ops->frequency_set)
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ops = dpll_pin_ops(ref);
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if (!ops->frequency_set || !ops->frequency_get) {
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NL_SET_ERR_MSG(extack, "frequency set not supported by the device");
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return -EOPNOTSUPP;
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}
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}
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ref = dpll_xa_ref_dpll_first(&pin->dpll_refs);
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ops = dpll_pin_ops(ref);
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dpll = ref->dpll;
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ret = ops->frequency_get(pin, dpll_pin_on_dpll_priv(dpll, pin), dpll,
|
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dpll_priv(dpll), &old_freq, extack);
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if (ret) {
|
||||
NL_SET_ERR_MSG(extack, "unable to get old frequency value");
|
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return ret;
|
||||
}
|
||||
if (freq == old_freq)
|
||||
return 0;
|
||||
|
||||
xa_for_each(&pin->dpll_refs, i, ref) {
|
||||
ops = dpll_pin_ops(ref);
|
||||
dpll = ref->dpll;
|
||||
ret = ops->frequency_set(pin, dpll_pin_on_dpll_priv(dpll, pin),
|
||||
dpll, dpll_priv(dpll), freq, extack);
|
||||
if (ret)
|
||||
return ret;
|
||||
if (ret) {
|
||||
failed = ref;
|
||||
NL_SET_ERR_MSG_FMT(extack, "frequency set failed for dpll_id:%u",
|
||||
dpll->id);
|
||||
goto rollback;
|
||||
}
|
||||
}
|
||||
__dpll_pin_change_ntf(pin);
|
||||
|
||||
return 0;
|
||||
|
||||
rollback:
|
||||
xa_for_each(&pin->dpll_refs, i, ref) {
|
||||
if (ref == failed)
|
||||
break;
|
||||
ops = dpll_pin_ops(ref);
|
||||
dpll = ref->dpll;
|
||||
if (ops->frequency_set(pin, dpll_pin_on_dpll_priv(dpll, pin),
|
||||
dpll, dpll_priv(dpll), old_freq, extack))
|
||||
NL_SET_ERR_MSG(extack, "set frequency rollback failed");
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int
|
||||
|
@ -705,6 +798,78 @@ dpll_pin_direction_set(struct dpll_pin *pin, struct dpll_device *dpll,
|
|||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
dpll_pin_phase_adj_set(struct dpll_pin *pin, struct nlattr *phase_adj_attr,
|
||||
struct netlink_ext_ack *extack)
|
||||
{
|
||||
struct dpll_pin_ref *ref, *failed;
|
||||
const struct dpll_pin_ops *ops;
|
||||
s32 phase_adj, old_phase_adj;
|
||||
struct dpll_device *dpll;
|
||||
unsigned long i;
|
||||
int ret;
|
||||
|
||||
phase_adj = nla_get_s32(phase_adj_attr);
|
||||
if (phase_adj > pin->prop->phase_range.max ||
|
||||
phase_adj < pin->prop->phase_range.min) {
|
||||
NL_SET_ERR_MSG_ATTR(extack, phase_adj_attr,
|
||||
"phase adjust value not supported");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
xa_for_each(&pin->dpll_refs, i, ref) {
|
||||
ops = dpll_pin_ops(ref);
|
||||
if (!ops->phase_adjust_set || !ops->phase_adjust_get) {
|
||||
NL_SET_ERR_MSG(extack, "phase adjust not supported");
|
||||
return -EOPNOTSUPP;
|
||||
}
|
||||
}
|
||||
ref = dpll_xa_ref_dpll_first(&pin->dpll_refs);
|
||||
ops = dpll_pin_ops(ref);
|
||||
dpll = ref->dpll;
|
||||
ret = ops->phase_adjust_get(pin, dpll_pin_on_dpll_priv(dpll, pin),
|
||||
dpll, dpll_priv(dpll), &old_phase_adj,
|
||||
extack);
|
||||
if (ret) {
|
||||
NL_SET_ERR_MSG(extack, "unable to get old phase adjust value");
|
||||
return ret;
|
||||
}
|
||||
if (phase_adj == old_phase_adj)
|
||||
return 0;
|
||||
|
||||
xa_for_each(&pin->dpll_refs, i, ref) {
|
||||
ops = dpll_pin_ops(ref);
|
||||
dpll = ref->dpll;
|
||||
ret = ops->phase_adjust_set(pin,
|
||||
dpll_pin_on_dpll_priv(dpll, pin),
|
||||
dpll, dpll_priv(dpll), phase_adj,
|
||||
extack);
|
||||
if (ret) {
|
||||
failed = ref;
|
||||
NL_SET_ERR_MSG_FMT(extack,
|
||||
"phase adjust set failed for dpll_id:%u",
|
||||
dpll->id);
|
||||
goto rollback;
|
||||
}
|
||||
}
|
||||
__dpll_pin_change_ntf(pin);
|
||||
|
||||
return 0;
|
||||
|
||||
rollback:
|
||||
xa_for_each(&pin->dpll_refs, i, ref) {
|
||||
if (ref == failed)
|
||||
break;
|
||||
ops = dpll_pin_ops(ref);
|
||||
dpll = ref->dpll;
|
||||
if (ops->phase_adjust_set(pin, dpll_pin_on_dpll_priv(dpll, pin),
|
||||
dpll, dpll_priv(dpll), old_phase_adj,
|
||||
extack))
|
||||
NL_SET_ERR_MSG(extack, "set phase adjust rollback failed");
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int
|
||||
dpll_pin_parent_device_set(struct dpll_pin *pin, struct nlattr *parent_nest,
|
||||
struct netlink_ext_ack *extack)
|
||||
|
@ -793,6 +958,11 @@ dpll_pin_set_from_nlattr(struct dpll_pin *pin, struct genl_info *info)
|
|||
if (ret)
|
||||
return ret;
|
||||
break;
|
||||
case DPLL_A_PIN_PHASE_ADJUST:
|
||||
ret = dpll_pin_phase_adj_set(pin, a, info->extack);
|
||||
if (ret)
|
||||
return ret;
|
||||
break;
|
||||
case DPLL_A_PIN_PARENT_DEVICE:
|
||||
ret = dpll_pin_parent_device_set(pin, a, info->extack);
|
||||
if (ret)
|
||||
|
|
|
@ -11,11 +11,12 @@
|
|||
#include <uapi/linux/dpll.h>
|
||||
|
||||
/* Common nested types */
|
||||
const struct nla_policy dpll_pin_parent_device_nl_policy[DPLL_A_PIN_STATE + 1] = {
|
||||
const struct nla_policy dpll_pin_parent_device_nl_policy[DPLL_A_PIN_PHASE_OFFSET + 1] = {
|
||||
[DPLL_A_PIN_PARENT_ID] = { .type = NLA_U32, },
|
||||
[DPLL_A_PIN_DIRECTION] = NLA_POLICY_RANGE(NLA_U32, 1, 2),
|
||||
[DPLL_A_PIN_PRIO] = { .type = NLA_U32, },
|
||||
[DPLL_A_PIN_STATE] = NLA_POLICY_RANGE(NLA_U32, 1, 3),
|
||||
[DPLL_A_PIN_PHASE_OFFSET] = { .type = NLA_S64, },
|
||||
};
|
||||
|
||||
const struct nla_policy dpll_pin_parent_pin_nl_policy[DPLL_A_PIN_STATE + 1] = {
|
||||
|
@ -61,7 +62,7 @@ static const struct nla_policy dpll_pin_get_dump_nl_policy[DPLL_A_PIN_ID + 1] =
|
|||
};
|
||||
|
||||
/* DPLL_CMD_PIN_SET - do */
|
||||
static const struct nla_policy dpll_pin_set_nl_policy[DPLL_A_PIN_PARENT_PIN + 1] = {
|
||||
static const struct nla_policy dpll_pin_set_nl_policy[DPLL_A_PIN_PHASE_ADJUST + 1] = {
|
||||
[DPLL_A_PIN_ID] = { .type = NLA_U32, },
|
||||
[DPLL_A_PIN_FREQUENCY] = { .type = NLA_U64, },
|
||||
[DPLL_A_PIN_DIRECTION] = NLA_POLICY_RANGE(NLA_U32, 1, 2),
|
||||
|
@ -69,6 +70,7 @@ static const struct nla_policy dpll_pin_set_nl_policy[DPLL_A_PIN_PARENT_PIN + 1]
|
|||
[DPLL_A_PIN_STATE] = NLA_POLICY_RANGE(NLA_U32, 1, 3),
|
||||
[DPLL_A_PIN_PARENT_DEVICE] = NLA_POLICY_NESTED(dpll_pin_parent_device_nl_policy),
|
||||
[DPLL_A_PIN_PARENT_PIN] = NLA_POLICY_NESTED(dpll_pin_parent_pin_nl_policy),
|
||||
[DPLL_A_PIN_PHASE_ADJUST] = { .type = NLA_S32, },
|
||||
};
|
||||
|
||||
/* Ops table for dpll */
|
||||
|
@ -140,7 +142,7 @@ static const struct genl_split_ops dpll_nl_ops[] = {
|
|||
.doit = dpll_nl_pin_set_doit,
|
||||
.post_doit = dpll_pin_post_doit,
|
||||
.policy = dpll_pin_set_nl_policy,
|
||||
.maxattr = DPLL_A_PIN_PARENT_PIN,
|
||||
.maxattr = DPLL_A_PIN_PHASE_ADJUST,
|
||||
.flags = GENL_ADMIN_PERM | GENL_CMD_CAP_DO,
|
||||
},
|
||||
};
|
||||
|
|
|
@ -12,7 +12,7 @@
|
|||
#include <uapi/linux/dpll.h>
|
||||
|
||||
/* Common nested types */
|
||||
extern const struct nla_policy dpll_pin_parent_device_nl_policy[DPLL_A_PIN_STATE + 1];
|
||||
extern const struct nla_policy dpll_pin_parent_device_nl_policy[DPLL_A_PIN_PHASE_OFFSET + 1];
|
||||
extern const struct nla_policy dpll_pin_parent_pin_nl_policy[DPLL_A_PIN_STATE + 1];
|
||||
|
||||
int dpll_lock_doit(const struct genl_split_ops *ops, struct sk_buff *skb,
|
||||
|
|
|
@ -878,6 +878,199 @@ ice_dpll_output_direction(const struct dpll_pin *pin, void *pin_priv,
|
|||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* ice_dpll_pin_phase_adjust_get - callback for get pin phase adjust value
|
||||
* @pin: pointer to a pin
|
||||
* @pin_priv: private data pointer passed on pin registration
|
||||
* @dpll: registered dpll pointer
|
||||
* @dpll_priv: private data pointer passed on dpll registration
|
||||
* @phase_adjust: on success holds pin phase_adjust value
|
||||
* @extack: error reporting
|
||||
*
|
||||
* Dpll subsystem callback. Handler for getting phase adjust value of a pin.
|
||||
*
|
||||
* Context: Acquires pf->dplls.lock
|
||||
* Return:
|
||||
* * 0 - success
|
||||
* * negative - error
|
||||
*/
|
||||
static int
|
||||
ice_dpll_pin_phase_adjust_get(const struct dpll_pin *pin, void *pin_priv,
|
||||
const struct dpll_device *dpll, void *dpll_priv,
|
||||
s32 *phase_adjust,
|
||||
struct netlink_ext_ack *extack)
|
||||
{
|
||||
struct ice_dpll_pin *p = pin_priv;
|
||||
struct ice_pf *pf = p->pf;
|
||||
|
||||
mutex_lock(&pf->dplls.lock);
|
||||
*phase_adjust = p->phase_adjust;
|
||||
mutex_unlock(&pf->dplls.lock);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* ice_dpll_pin_phase_adjust_set - helper for setting a pin phase adjust value
|
||||
* @pin: pointer to a pin
|
||||
* @pin_priv: private data pointer passed on pin registration
|
||||
* @dpll: registered dpll pointer
|
||||
* @dpll_priv: private data pointer passed on dpll registration
|
||||
* @phase_adjust: phase_adjust to be set
|
||||
* @extack: error reporting
|
||||
* @type: type of a pin
|
||||
*
|
||||
* Helper for dpll subsystem callback. Handler for setting phase adjust value
|
||||
* of a pin.
|
||||
*
|
||||
* Context: Acquires pf->dplls.lock
|
||||
* Return:
|
||||
* * 0 - success
|
||||
* * negative - error
|
||||
*/
|
||||
static int
|
||||
ice_dpll_pin_phase_adjust_set(const struct dpll_pin *pin, void *pin_priv,
|
||||
const struct dpll_device *dpll, void *dpll_priv,
|
||||
s32 phase_adjust,
|
||||
struct netlink_ext_ack *extack,
|
||||
enum ice_dpll_pin_type type)
|
||||
{
|
||||
struct ice_dpll_pin *p = pin_priv;
|
||||
struct ice_dpll *d = dpll_priv;
|
||||
struct ice_pf *pf = d->pf;
|
||||
u8 flag, flags_en = 0;
|
||||
int ret;
|
||||
|
||||
mutex_lock(&pf->dplls.lock);
|
||||
switch (type) {
|
||||
case ICE_DPLL_PIN_TYPE_INPUT:
|
||||
flag = ICE_AQC_SET_CGU_IN_CFG_FLG1_UPDATE_DELAY;
|
||||
if (p->flags[0] & ICE_AQC_GET_CGU_IN_CFG_FLG2_ESYNC_EN)
|
||||
flags_en |= ICE_AQC_SET_CGU_IN_CFG_FLG2_ESYNC_EN;
|
||||
if (p->flags[0] & ICE_AQC_GET_CGU_IN_CFG_FLG2_INPUT_EN)
|
||||
flags_en |= ICE_AQC_SET_CGU_IN_CFG_FLG2_INPUT_EN;
|
||||
ret = ice_aq_set_input_pin_cfg(&pf->hw, p->idx, flag, flags_en,
|
||||
0, phase_adjust);
|
||||
break;
|
||||
case ICE_DPLL_PIN_TYPE_OUTPUT:
|
||||
flag = ICE_AQC_SET_CGU_OUT_CFG_UPDATE_PHASE;
|
||||
if (p->flags[0] & ICE_AQC_GET_CGU_OUT_CFG_OUT_EN)
|
||||
flag |= ICE_AQC_SET_CGU_OUT_CFG_OUT_EN;
|
||||
if (p->flags[0] & ICE_AQC_GET_CGU_OUT_CFG_ESYNC_EN)
|
||||
flag |= ICE_AQC_SET_CGU_OUT_CFG_ESYNC_EN;
|
||||
ret = ice_aq_set_output_pin_cfg(&pf->hw, p->idx, flag, 0, 0,
|
||||
phase_adjust);
|
||||
break;
|
||||
default:
|
||||
ret = -EINVAL;
|
||||
}
|
||||
if (!ret)
|
||||
p->phase_adjust = phase_adjust;
|
||||
mutex_unlock(&pf->dplls.lock);
|
||||
if (ret)
|
||||
NL_SET_ERR_MSG_FMT(extack,
|
||||
"err:%d %s failed to set pin phase_adjust:%d for pin:%u on dpll:%u\n",
|
||||
ret,
|
||||
ice_aq_str(pf->hw.adminq.sq_last_status),
|
||||
phase_adjust, p->idx, d->dpll_idx);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* ice_dpll_input_phase_adjust_set - callback for set input pin phase adjust
|
||||
* @pin: pointer to a pin
|
||||
* @pin_priv: private data pointer passed on pin registration
|
||||
* @dpll: registered dpll pointer
|
||||
* @dpll_priv: private data pointer passed on dpll registration
|
||||
* @phase_adjust: phase_adjust to be set
|
||||
* @extack: error reporting
|
||||
*
|
||||
* Dpll subsystem callback. Wraps a handler for setting phase adjust on input
|
||||
* pin.
|
||||
*
|
||||
* Context: Calls a function which acquires pf->dplls.lock
|
||||
* Return:
|
||||
* * 0 - success
|
||||
* * negative - error
|
||||
*/
|
||||
static int
|
||||
ice_dpll_input_phase_adjust_set(const struct dpll_pin *pin, void *pin_priv,
|
||||
const struct dpll_device *dpll, void *dpll_priv,
|
||||
s32 phase_adjust,
|
||||
struct netlink_ext_ack *extack)
|
||||
{
|
||||
return ice_dpll_pin_phase_adjust_set(pin, pin_priv, dpll, dpll_priv,
|
||||
phase_adjust, extack,
|
||||
ICE_DPLL_PIN_TYPE_INPUT);
|
||||
}
|
||||
|
||||
/**
|
||||
* ice_dpll_output_phase_adjust_set - callback for set output pin phase adjust
|
||||
* @pin: pointer to a pin
|
||||
* @pin_priv: private data pointer passed on pin registration
|
||||
* @dpll: registered dpll pointer
|
||||
* @dpll_priv: private data pointer passed on dpll registration
|
||||
* @phase_adjust: phase_adjust to be set
|
||||
* @extack: error reporting
|
||||
*
|
||||
* Dpll subsystem callback. Wraps a handler for setting phase adjust on output
|
||||
* pin.
|
||||
*
|
||||
* Context: Calls a function which acquires pf->dplls.lock
|
||||
* Return:
|
||||
* * 0 - success
|
||||
* * negative - error
|
||||
*/
|
||||
static int
|
||||
ice_dpll_output_phase_adjust_set(const struct dpll_pin *pin, void *pin_priv,
|
||||
const struct dpll_device *dpll, void *dpll_priv,
|
||||
s32 phase_adjust,
|
||||
struct netlink_ext_ack *extack)
|
||||
{
|
||||
return ice_dpll_pin_phase_adjust_set(pin, pin_priv, dpll, dpll_priv,
|
||||
phase_adjust, extack,
|
||||
ICE_DPLL_PIN_TYPE_OUTPUT);
|
||||
}
|
||||
|
||||
#define ICE_DPLL_PHASE_OFFSET_DIVIDER 100
|
||||
#define ICE_DPLL_PHASE_OFFSET_FACTOR \
|
||||
(DPLL_PHASE_OFFSET_DIVIDER / ICE_DPLL_PHASE_OFFSET_DIVIDER)
|
||||
/**
|
||||
* ice_dpll_phase_offset_get - callback for get dpll phase shift value
|
||||
* @pin: pointer to a pin
|
||||
* @pin_priv: private data pointer passed on pin registration
|
||||
* @dpll: registered dpll pointer
|
||||
* @dpll_priv: private data pointer passed on dpll registration
|
||||
* @phase_offset: on success holds pin phase_offset value
|
||||
* @extack: error reporting
|
||||
*
|
||||
* Dpll subsystem callback. Handler for getting phase shift value between
|
||||
* dpll's input and output.
|
||||
*
|
||||
* Context: Acquires pf->dplls.lock
|
||||
* Return:
|
||||
* * 0 - success
|
||||
* * negative - error
|
||||
*/
|
||||
static int
|
||||
ice_dpll_phase_offset_get(const struct dpll_pin *pin, void *pin_priv,
|
||||
const struct dpll_device *dpll, void *dpll_priv,
|
||||
s64 *phase_offset, struct netlink_ext_ack *extack)
|
||||
{
|
||||
struct ice_dpll *d = dpll_priv;
|
||||
struct ice_pf *pf = d->pf;
|
||||
|
||||
mutex_lock(&pf->dplls.lock);
|
||||
if (d->active_input == pin)
|
||||
*phase_offset = d->phase_offset * ICE_DPLL_PHASE_OFFSET_FACTOR;
|
||||
else
|
||||
*phase_offset = 0;
|
||||
mutex_unlock(&pf->dplls.lock);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* ice_dpll_rclk_state_on_pin_set - set a state on rclk pin
|
||||
* @pin: pointer to a pin
|
||||
|
@ -993,6 +1186,9 @@ static const struct dpll_pin_ops ice_dpll_input_ops = {
|
|||
.prio_get = ice_dpll_input_prio_get,
|
||||
.prio_set = ice_dpll_input_prio_set,
|
||||
.direction_get = ice_dpll_input_direction,
|
||||
.phase_adjust_get = ice_dpll_pin_phase_adjust_get,
|
||||
.phase_adjust_set = ice_dpll_input_phase_adjust_set,
|
||||
.phase_offset_get = ice_dpll_phase_offset_get,
|
||||
};
|
||||
|
||||
static const struct dpll_pin_ops ice_dpll_output_ops = {
|
||||
|
@ -1001,6 +1197,8 @@ static const struct dpll_pin_ops ice_dpll_output_ops = {
|
|||
.state_on_dpll_get = ice_dpll_output_state_get,
|
||||
.state_on_dpll_set = ice_dpll_output_state_set,
|
||||
.direction_get = ice_dpll_output_direction,
|
||||
.phase_adjust_get = ice_dpll_pin_phase_adjust_get,
|
||||
.phase_adjust_set = ice_dpll_output_phase_adjust_set,
|
||||
};
|
||||
|
||||
static const struct dpll_device_ops ice_dpll_ops = {
|
||||
|
@ -1031,6 +1229,8 @@ static u64 ice_generate_clock_id(struct ice_pf *pf)
|
|||
*/
|
||||
static void ice_dpll_notify_changes(struct ice_dpll *d)
|
||||
{
|
||||
bool pin_notified = false;
|
||||
|
||||
if (d->prev_dpll_state != d->dpll_state) {
|
||||
d->prev_dpll_state = d->dpll_state;
|
||||
dpll_device_change_ntf(d->dpll);
|
||||
|
@ -1039,7 +1239,14 @@ static void ice_dpll_notify_changes(struct ice_dpll *d)
|
|||
if (d->prev_input)
|
||||
dpll_pin_change_ntf(d->prev_input);
|
||||
d->prev_input = d->active_input;
|
||||
if (d->active_input)
|
||||
if (d->active_input) {
|
||||
dpll_pin_change_ntf(d->active_input);
|
||||
pin_notified = true;
|
||||
}
|
||||
}
|
||||
if (d->prev_phase_offset != d->phase_offset) {
|
||||
d->prev_phase_offset = d->phase_offset;
|
||||
if (!pin_notified && d->active_input)
|
||||
dpll_pin_change_ntf(d->active_input);
|
||||
}
|
||||
}
|
||||
|
@ -1065,7 +1272,7 @@ ice_dpll_update_state(struct ice_pf *pf, struct ice_dpll *d, bool init)
|
|||
|
||||
ret = ice_get_cgu_state(&pf->hw, d->dpll_idx, d->prev_dpll_state,
|
||||
&d->input_idx, &d->ref_state, &d->eec_mode,
|
||||
&d->phase_shift, &d->dpll_state);
|
||||
&d->phase_offset, &d->dpll_state);
|
||||
|
||||
dev_dbg(ice_pf_to_dev(pf),
|
||||
"update dpll=%d, prev_src_idx:%u, src_idx:%u, state:%d, prev:%d mode:%d\n",
|
||||
|
@ -1656,6 +1863,15 @@ ice_dpll_init_info_direct_pins(struct ice_pf *pf,
|
|||
return ret;
|
||||
pins[i].prop.capabilities |=
|
||||
DPLL_PIN_CAPABILITIES_PRIORITY_CAN_CHANGE;
|
||||
pins[i].prop.phase_range.min =
|
||||
pf->dplls.input_phase_adj_max;
|
||||
pins[i].prop.phase_range.max =
|
||||
-pf->dplls.input_phase_adj_max;
|
||||
} else {
|
||||
pins[i].prop.phase_range.min =
|
||||
pf->dplls.output_phase_adj_max;
|
||||
pins[i].prop.phase_range.max =
|
||||
-pf->dplls.output_phase_adj_max;
|
||||
}
|
||||
pins[i].prop.capabilities |=
|
||||
DPLL_PIN_CAPABILITIES_STATE_CAN_CHANGE;
|
||||
|
|
|
@ -19,6 +19,7 @@
|
|||
* @state: state of a pin
|
||||
* @prop: pin properties
|
||||
* @freq: current frequency of a pin
|
||||
* @phase_adjust: current phase adjust value
|
||||
*/
|
||||
struct ice_dpll_pin {
|
||||
struct dpll_pin *pin;
|
||||
|
@ -30,6 +31,7 @@ struct ice_dpll_pin {
|
|||
u8 state[ICE_DPLL_RCLK_NUM_MAX];
|
||||
struct dpll_pin_properties prop;
|
||||
u32 freq;
|
||||
s32 phase_adjust;
|
||||
};
|
||||
|
||||
/** ice_dpll - store info required for DPLL control
|
||||
|
@ -40,7 +42,8 @@ struct ice_dpll_pin {
|
|||
* @prev_input_idx: previously selected input index
|
||||
* @ref_state: state of dpll reference signals
|
||||
* @eec_mode: eec_mode dpll is configured for
|
||||
* @phase_shift: phase shift delay of a dpll
|
||||
* @phase_offset: phase offset of active pin vs dpll signal
|
||||
* @prev_phase_offset: previous phase offset of active pin vs dpll signal
|
||||
* @input_prio: priorities of each input
|
||||
* @dpll_state: current dpll sync state
|
||||
* @prev_dpll_state: last dpll sync state
|
||||
|
@ -55,7 +58,8 @@ struct ice_dpll {
|
|||
u8 prev_input_idx;
|
||||
u8 ref_state;
|
||||
u8 eec_mode;
|
||||
s64 phase_shift;
|
||||
s64 phase_offset;
|
||||
s64 prev_phase_offset;
|
||||
u8 *input_prio;
|
||||
enum dpll_lock_status dpll_state;
|
||||
enum dpll_lock_status prev_dpll_state;
|
||||
|
@ -78,6 +82,8 @@ struct ice_dpll {
|
|||
* @cgu_state_acq_err_num: number of errors returned during periodic work
|
||||
* @base_rclk_idx: idx of first pin used for clock revocery pins
|
||||
* @clock_id: clock_id of dplls
|
||||
* @input_phase_adj_max: max phase adjust value for an input pins
|
||||
* @output_phase_adj_max: max phase adjust value for an output pins
|
||||
*/
|
||||
struct ice_dplls {
|
||||
struct kthread_worker *kworker;
|
||||
|
|
|
@ -68,6 +68,18 @@ struct dpll_pin_ops {
|
|||
int (*prio_set)(const struct dpll_pin *pin, void *pin_priv,
|
||||
const struct dpll_device *dpll, void *dpll_priv,
|
||||
const u32 prio, struct netlink_ext_ack *extack);
|
||||
int (*phase_offset_get)(const struct dpll_pin *pin, void *pin_priv,
|
||||
const struct dpll_device *dpll, void *dpll_priv,
|
||||
s64 *phase_offset,
|
||||
struct netlink_ext_ack *extack);
|
||||
int (*phase_adjust_get)(const struct dpll_pin *pin, void *pin_priv,
|
||||
const struct dpll_device *dpll, void *dpll_priv,
|
||||
s32 *phase_adjust,
|
||||
struct netlink_ext_ack *extack);
|
||||
int (*phase_adjust_set)(const struct dpll_pin *pin, void *pin_priv,
|
||||
const struct dpll_device *dpll, void *dpll_priv,
|
||||
const s32 phase_adjust,
|
||||
struct netlink_ext_ack *extack);
|
||||
};
|
||||
|
||||
struct dpll_pin_frequency {
|
||||
|
@ -91,6 +103,11 @@ struct dpll_pin_frequency {
|
|||
#define DPLL_PIN_FREQUENCY_DCF77 \
|
||||
DPLL_PIN_FREQUENCY(DPLL_PIN_FREQUENCY_77_5_KHZ)
|
||||
|
||||
struct dpll_pin_phase_adjust_range {
|
||||
s32 min;
|
||||
s32 max;
|
||||
};
|
||||
|
||||
struct dpll_pin_properties {
|
||||
const char *board_label;
|
||||
const char *panel_label;
|
||||
|
@ -99,6 +116,7 @@ struct dpll_pin_properties {
|
|||
unsigned long capabilities;
|
||||
u32 freq_supported_num;
|
||||
struct dpll_pin_frequency *freq_supported;
|
||||
struct dpll_pin_phase_adjust_range phase_range;
|
||||
};
|
||||
|
||||
#if IS_ENABLED(CONFIG_DPLL)
|
||||
|
|
|
@ -138,6 +138,8 @@ enum dpll_pin_capabilities {
|
|||
DPLL_PIN_CAPABILITIES_STATE_CAN_CHANGE = 4,
|
||||
};
|
||||
|
||||
#define DPLL_PHASE_OFFSET_DIVIDER 1000
|
||||
|
||||
enum dpll_a {
|
||||
DPLL_A_ID = 1,
|
||||
DPLL_A_MODULE_NAME,
|
||||
|
@ -173,6 +175,10 @@ enum dpll_a_pin {
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|||
DPLL_A_PIN_CAPABILITIES,
|
||||
DPLL_A_PIN_PARENT_DEVICE,
|
||||
DPLL_A_PIN_PARENT_PIN,
|
||||
DPLL_A_PIN_PHASE_ADJUST_MIN,
|
||||
DPLL_A_PIN_PHASE_ADJUST_MAX,
|
||||
DPLL_A_PIN_PHASE_ADJUST,
|
||||
DPLL_A_PIN_PHASE_OFFSET,
|
||||
|
||||
__DPLL_A_PIN_MAX,
|
||||
DPLL_A_PIN_MAX = (__DPLL_A_PIN_MAX - 1)
|
||||
|
|
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Reference in a new issue