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Renesas ARM Based SoC DT Updates for v4.13

Browse source 
* Switch to panel-lvds bindings for Mitsubishi panels
 * Clean up PFC node names
 * Enable UHS-I SDR-50 and SDR-104 on r8a7793/Gose
 * Add GyroADC clock and device for r8a7791 SoC
 * Add USB clocks to device tree for r7s72100 SoC
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Merge tag 'renesas-dt-for-v4.13' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt

Renesas ARM Based SoC DT Updates for v4.13

* Switch to panel-lvds bindings for Mitsubishi panels
* Clean up PFC node names
* Enable UHS-I SDR-50 and SDR-104 on r8a7793/Gose
* Add GyroADC clock and device for r8a7791 SoC
* Add USB clocks to device tree for r7s72100 SoC

* tag 'renesas-dt-for-v4.13' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
  ARM: dts: renesas: Switch to panel-lvds bindings for Mitsubishi panels
  ARM: dts: gose: Enable UHS-I SDR-50 and SDR-104
  ARM: dts: r8a7793: set maximum frequency for SDHI clocks
  ARM: dts: r8a7791: Add GyroADC clock and device node
  ARM: dts: r7s72100: add usb clocks to device tree
  ARM: dts: sh73a0: update PFC node name to pin-controller
  ARM: dts: r8a7793: update PFC node name to pin-controller
  ARM: dts: r8a7791: update PFC node name to pin-controller
  ARM: dts: r8a7790: update PFC node name to pin-controller
  ARM: dts: r8a7779: update PFC node name to pin-controller
  ARM: dts: r8a7778: update PFC node name to pin-controller
  ARM: dts: r8a7740: update PFC node name to pin-controller
  ARM: dts: r8a73a4: update PFC node name to pin-controller
  ARM: dts: emev2: update PFC node name to pin-controller
  ARM: dts: r7s72100: add USB bit definitions
  ARM: dts: r7s72100: add Renesas RZ/A1 pinctrl header
  ARM: dts: r8a7791: add GyroADC clock

Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson 2017-06-01 17:24:15 -07:00
commit 996e559a2d
16 changed files with 82 additions and 18 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
arch/arm/boot/dts/emev2.dtsi
View file

@ -197,7 +197,7 @@ uart3: serial@e1050000 {
clock-names = "sclk";
};
pfc: pfc@e0140200 {
pfc: pin-controller@e0140200 {
compatible = "renesas,pfc-emev2";
reg = <0xe0140200 0x100>;
};

6
arch/arm/boot/dts/r7s72100.dtsi
View file

@ -144,9 +144,9 @@ mstp7_clks: mstp7_clks@fcfe0430 {
#clock-cells = <1>;
compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
reg = <0xfcfe0430 4>;
clocks = <&b_clk>;
clock-indices = <R7S72100_CLK_ETHER>;
clock-output-names = "ether";
clocks = <&b_clk>, <&p1_clk>, <&p1_clk>;
clock-indices = <R7S72100_CLK_ETHER R7S72100_CLK_USB0 R7S72100_CLK_USB1>;
clock-output-names = "ether", "usb0", "usb1";
};
mstp8_clks: mstp8_clks@fcfe0434 {

2
arch/arm/boot/dts/r8a73a4.dtsi
View file

@ -219,7 +219,7 @@ irqc1: interrupt-controller@e61c0200 {
power-domains = <&pd_c4>;
};
pfc: pfc@e6050000 {
pfc: pin-controller@e6050000 {
compatible = "renesas,pfc-r8a73a4";
reg = <0 0xe6050000 0 0x9000>;
gpio-controller;

2
arch/arm/boot/dts/r8a7740.dtsi
View file

@ -299,7 +299,7 @@ scifb: serial@e6c30000 {
status = "disabled";
};
pfc: pfc@e6050000 {
pfc: pin-controller@e6050000 {
compatible = "renesas,pfc-r8a7740";
reg = <0xe6050000 0x8000>,
<0xe605800c 0x20>;

2
arch/arm/boot/dts/r8a7778.dtsi
View file

@ -142,7 +142,7 @@ gpio4: gpio@ffc44000 {
interrupt-controller;
};
pfc: pfc@fffc0000 {
pfc: pin-controller@fffc0000 {
compatible = "renesas,pfc-r8a7778";
reg = <0xfffc0000 0x118>;
};

2
arch/arm/boot/dts/r8a7779.dtsi
View file

@ -286,7 +286,7 @@ scif5: serial@ffe45000 {
status = "disabled";
};
pfc: pfc@fffc0000 {
pfc: pin-controller@fffc0000 {
compatible = "renesas,pfc-r8a7779";
reg = <0xfffc0000 0x23c>;
};

2
arch/arm/boot/dts/r8a7790.dtsi
View file

@ -614,7 +614,7 @@ mmcif1: mmc@ee220000 {
max-frequency = <97500000>;
};
pfc: pfc@e6060000 {
pfc: pin-controller@e6060000 {
compatible = "renesas,pfc-r8a7790";
reg = <0 0xe6060000 0 0x250>;
};

16
arch/arm/boot/dts/r8a7791.dtsi
View file

@ -562,7 +562,7 @@ i2c8: i2c@e6510000 {
status = "disabled";
};
pfc: pfc@e6060000 {
pfc: pin-controller@e6060000 {
compatible = "renesas,pfc-r8a7791";
reg = <0 0xe6060000 0 0x250>;
};
@ -776,6 +776,15 @@ scif1: serial@e6e68000 {
status = "disabled";
};
adc: adc@e6e54000 {
compatible = "renesas,r8a7791-gyroadc", "renesas,rcar-gyroadc";
reg = <0 0xe6e54000 0 64>;
clocks = <&mstp9_clks R8A7791_CLK_GYROADC>;
clock-names = "fck";
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
status = "disabled";
};
scif2: serial@e6e58000 {
compatible = "renesas,scif-r8a7791", "renesas,rcar-gen2-scif",
"renesas,scif";
@ -1425,13 +1434,15 @@ R8A7791_CLK_SATA1 R8A7791_CLK_SATA0
mstp9_clks: mstp9_clks@e6150994 {
compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
clocks = <&p_clk>,
<&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
<&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
<&p_clk>, <&p_clk>, <&cpg_clocks R8A7791_CLK_QSPI>, <&hp_clk>,
<&cp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>,
<&hp_clk>, <&hp_clk>;
#clock-cells = <1>;
clock-indices = <
R8A7791_CLK_GYROADC
R8A7791_CLK_GPIO7 R8A7791_CLK_GPIO6 R8A7791_CLK_GPIO5 R8A7791_CLK_GPIO4
R8A7791_CLK_GPIO3 R8A7791_CLK_GPIO2 R8A7791_CLK_GPIO1 R8A7791_CLK_GPIO0
R8A7791_CLK_RCAN1 R8A7791_CLK_RCAN0 R8A7791_CLK_QSPI_MOD R8A7791_CLK_I2C5
@ -1439,6 +1450,7 @@ R8A7791_CLK_IICDVFS R8A7791_CLK_I2C4 R8A7791_CLK_I2C3 R8A7791_CLK_I2C2
R8A7791_CLK_I2C1 R8A7791_CLK_I2C0
>;
clock-output-names =
"gyroadc",
"gpio7", "gpio6", "gpio5", "gpio4", "gpio3", "gpio2", "gpio1", "gpio0",
"rcan1", "rcan0", "qspi_mod", "i2c5", "i2c6", "i2c4", "i2c3", "i2c2",
"i2c1", "i2c0";

34
arch/arm/boot/dts/r8a7793-gose.dts
View file

@ -348,16 +348,37 @@ phy1_pins: phy1 {
sdhi0_pins: sd0 {
groups = "sdhi0_data4", "sdhi0_ctrl";
function = "sdhi0";
power-source = <3300>;
};
sdhi0_pins_uhs: sd0_uhs {
groups = "sdhi0_data4", "sdhi0_ctrl";
function = "sdhi0";
power-source = <1800>;
};
sdhi1_pins: sd1 {
groups = "sdhi1_data4", "sdhi1_ctrl";
function = "sdhi1";
power-source = <3300>;
};
sdhi1_pins_uhs: sd1_uhs {
groups = "sdhi1_data4", "sdhi1_ctrl";
function = "sdhi1";
power-source = <1800>;
};
sdhi2_pins: sd2 {
groups = "sdhi2_data4", "sdhi2_ctrl";
function = "sdhi2";
power-source = <3300>;
};
sdhi2_pins_uhs: sd2_uhs {
groups = "sdhi2_data4", "sdhi2_ctrl";
function = "sdhi2";
power-source = <1800>;
};
qspi_pins: qspi {
@ -416,33 +437,40 @@ &scif_clk {
&sdhi0 {
pinctrl-0 = <&sdhi0_pins>;
pinctrl-names = "default";
pinctrl-1 = <&sdhi0_pins_uhs>;
pinctrl-names = "default", "state_uhs";
vmmc-supply = <&vcc_sdhi0>;
vqmmc-supply = <&vccq_sdhi0>;
cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>;
sd-uhs-sdr50;
sd-uhs-sdr104;
status = "okay";
};
&sdhi1 {
pinctrl-0 = <&sdhi1_pins>;
pinctrl-names = "default";
pinctrl-1 = <&sdhi1_pins_uhs>;
pinctrl-names = "default", "state_uhs";
vmmc-supply = <&vcc_sdhi1>;
vqmmc-supply = <&vccq_sdhi1>;
cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>;
sd-uhs-sdr50;
status = "okay";
};
&sdhi2 {
pinctrl-0 = <&sdhi2_pins>;
pinctrl-names = "default";
pinctrl-1 = <&sdhi2_pins_uhs>;
pinctrl-names = "default", "state_uhs";
vmmc-supply = <&vcc_sdhi2>;
vqmmc-supply = <&vccq_sdhi2>;
cd-gpios = <&gpio6 22 GPIO_ACTIVE_LOW>;
sd-uhs-sdr50;
status = "okay";
};

5
arch/arm/boot/dts/r8a7793.dtsi
View file

@ -529,7 +529,7 @@ i2c8: i2c@e6510000 {
status = "disabled";
};
pfc: pfc@e6060000 {
pfc: pin-controller@e6060000 {
compatible = "renesas,pfc-r8a7793";
reg = <0 0xe6060000 0 0x250>;
};
@ -542,6 +542,7 @@ sdhi0: sd@ee100000 {
dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
<&dmac1 0xcd>, <&dmac1 0xce>;
dma-names = "tx", "rx", "tx", "rx";
max-frequency = <195000000>;
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
status = "disabled";
};
@ -554,6 +555,7 @@ sdhi1: sd@ee140000 {
dmas = <&dmac0 0xc1>, <&dmac0 0xc2>,
<&dmac1 0xc1>, <&dmac1 0xc2>;
dma-names = "tx", "rx", "tx", "rx";
max-frequency = <97500000>;
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
status = "disabled";
};
@ -566,6 +568,7 @@ sdhi2: sd@ee160000 {
dmas = <&dmac0 0xd3>, <&dmac0 0xd4>,
<&dmac1 0xd3>, <&dmac1 0xd4>;
dma-names = "tx", "rx", "tx", "rx";
max-frequency = <97500000>;
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
status = "disabled";
};

3
arch/arm/boot/dts/r8a77xx-aa104xd12-panel.dtsi
View file

@ -10,10 +10,11 @@
/ {
panel {
compatible = "mitsubishi,aa104xd12", "panel-dpi";
compatible = "mitsubishi,aa104xd12", "panel-lvds";
width-mm = <210>;
height-mm = <158>;
data-mapping = "jeida-18";
panel-timing {
/* 1024x768 @65Hz */

3
arch/arm/boot/dts/r8a77xx-aa121td01-panel.dtsi
View file

@ -10,10 +10,11 @@
/ {
panel {
compatible = "mitsubishi,aa121td01", "panel-dpi";
compatible = "mitsubishi,aa121td01", "panel-lvds";
width-mm = <261>;
height-mm = <163>;
data-mapping = "jeida-18";
panel-timing {
/* 1280x800 @60Hz */

2
arch/arm/boot/dts/sh73a0.dtsi
View file

@ -444,7 +444,7 @@ scifb: serial@e6c30000 {
status = "disabled";
};
pfc: pfc@e6050000 {
pfc: pin-controller@e6050000 {
compatible = "renesas,pfc-sh73a0";
reg = <0xe6050000 0x8000>,
<0xe605801c 0x1c>;

2
include/dt-bindings/clock/r7s72100-clock.h
View file

@ -34,6 +34,8 @@
/* MSTP7 */
#define R7S72100_CLK_ETHER 4
#define R7S72100_CLK_USB0 1
#define R7S72100_CLK_USB1 0
/* MSTP8 */
#define R7S72100_CLK_MMCIF 4

1
include/dt-bindings/clock/r8a7791-clock.h
View file

@ -109,6 +109,7 @@
#define R8A7791_CLK_SATA0 15
/* MSTP9 */
#define R8A7791_CLK_GYROADC 1
#define R8A7791_CLK_GPIO7 4
#define R8A7791_CLK_GPIO6 5
#define R8A7791_CLK_GPIO5 7

16
include/dt-bindings/pinctrl/r7s72100-pinctrl.h Normal file
View file

@ -0,0 +1,16 @@
/*
* Defines macros and constants for Renesas RZ/A1 pin controller pin
* muxing functions.
*/
#ifndef __DT_BINDINGS_PINCTRL_RENESAS_RZA1_H
#define __DT_BINDINGS_PINCTRL_RENESAS_RZA1_H
#define RZA1_PINS_PER_PORT 16
/*
* Create the pin index from its bank and position numbers and store in
* the upper 16 bits the alternate function identifier
*/
#define RZA1_PINMUX(b, p, f) ((b) * RZA1_PINS_PER_PORT + (p) | (f << 16))
#endif /* __DT_BINDINGS_PINCTRL_RENESAS_RZA1_H */