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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-08-25 02:09:42 +00:00
drm/i915/fdi: Improve FDI BW sharing between pipe B and C
At the moment modesetting pipe C on IVB will fail if pipe B uses 4 FDI lanes. Make the BW sharing more dynamic by trying to reduce pipe B's link bpp in this case, until pipe B uses only up to 2 FDI lanes. For this instead of the encoder compute config retry loop - which reduced link bpp only for the encoder's pipe - reduce the maximum link bpp for pipe B/C as required after all CRTC states are computed and recompute the CRTC states with the new bpp limit. Atm, all FDI encoder's compute config function returns an error if a BW constrain prevents increasing the pipe bpp value. The corresponding crtc_state->bw_constrained check can be replaced with checking crtc_state->max_link_bpp_x16, add TODO comments for this. SDVO is an exception where this case is only handled in the outer config retry loop, failing the modeset with a WARN, add a FIXME comment to handle this in the encoder code similarly to other encoders. v2: - Don't assume that a CRTC is already in the atomic state, while reducing its link bpp. - Add DocBook description to intel_fdi_atomic_check_link(). v3: - Enable BW management for FDI links in a separate patch. (Ville) v4: (Ville) - Fail the SDVO encoder config computation if it doesn't support the link bpp limit. - Add TODO: comments about checking link_bpp_x16 instead of bw_constrained. v5: - Replace link bpp limit check with a FIXME: comment in intel_sdvo_compute_config(). (Ville) Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> [Amended commit message wrt. changes in v5] Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230921195159.2646027-11-imre.deak@intel.com
This commit is contained in:
parent
8ca0b875c0
commit
998d2cd361
9 changed files with 140 additions and 40 deletions
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@ -16,6 +16,7 @@
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#include "intel_display_types.h"
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#include "intel_dp_aux.h"
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#include "intel_dpio_phy.h"
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#include "intel_fdi.h"
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#include "intel_fifo_underrun.h"
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#include "intel_hdmi.h"
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#include "intel_hotplug.h"
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@ -133,8 +134,11 @@ static int g4x_hdmi_compute_config(struct intel_encoder *encoder,
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struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
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struct drm_i915_private *i915 = to_i915(encoder->base.dev);
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if (HAS_PCH_SPLIT(i915))
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if (HAS_PCH_SPLIT(i915)) {
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crtc_state->has_pch_encoder = true;
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if (!intel_fdi_compute_pipe_bpp(crtc_state))
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return -EINVAL;
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}
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if (IS_G4X(i915))
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crtc_state->has_hdmi_sink = g4x_compute_has_hdmi_sink(state, crtc);
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@ -413,6 +413,9 @@ static int pch_crt_compute_config(struct intel_encoder *encoder,
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return -EINVAL;
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pipe_config->has_pch_encoder = true;
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if (!intel_fdi_compute_pipe_bpp(pipe_config))
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return -EINVAL;
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pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
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return 0;
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@ -435,10 +438,14 @@ static int hsw_crt_compute_config(struct intel_encoder *encoder,
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return -EINVAL;
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pipe_config->has_pch_encoder = true;
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if (!intel_fdi_compute_pipe_bpp(pipe_config))
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return -EINVAL;
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pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
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/* LPT FDI RX only supports 8bpc. */
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if (HAS_PCH_LPT(dev_priv)) {
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/* TODO: Check crtc_state->max_link_bpp_x16 instead of bw_constrained */
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if (pipe_config->bw_constrained && pipe_config->pipe_bpp < 24) {
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drm_dbg_kms(&dev_priv->drm,
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"LPT only supports 24bpp\n");
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@ -4655,7 +4655,6 @@ intel_modeset_pipe_config(struct intel_atomic_state *state,
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struct drm_connector_state *connector_state;
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int pipe_src_w, pipe_src_h;
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int base_bpp, ret, i;
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bool retry = true;
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crtc_state->cpu_transcoder = (enum transcoder) crtc->pipe;
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@ -4685,6 +4684,7 @@ intel_modeset_pipe_config(struct intel_atomic_state *state,
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"[CRTC:%d:%s] Link bpp limited to " BPP_X16_FMT "\n",
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crtc->base.base.id, crtc->base.name,
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BPP_X16_ARGS(crtc_state->max_link_bpp_x16));
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crtc_state->bw_constrained = true;
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}
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base_bpp = crtc_state->pipe_bpp;
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@ -4728,7 +4728,6 @@ intel_modeset_pipe_config(struct intel_atomic_state *state,
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crtc_state->output_types |= BIT(encoder->type);
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}
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encoder_retry:
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/* Ensure the port clock defaults are reset when retrying. */
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crtc_state->port_clock = 0;
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crtc_state->pixel_multiplier = 1;
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@ -4768,17 +4767,6 @@ intel_modeset_pipe_config(struct intel_atomic_state *state,
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ret = intel_crtc_compute_config(state, crtc);
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if (ret == -EDEADLK)
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return ret;
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if (ret == -EAGAIN) {
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if (drm_WARN(&i915->drm, !retry,
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"[CRTC:%d:%s] loop in pipe configuration computation\n",
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crtc->base.base.id, crtc->base.name))
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return -EINVAL;
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drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] bw constrained, retrying\n",
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crtc->base.base.id, crtc->base.name);
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retry = false;
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goto encoder_retry;
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}
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if (ret < 0) {
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drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] config failure: %d\n",
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crtc->base.base.id, crtc->base.name, ret);
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@ -2219,7 +2219,8 @@ intel_dp_compute_config_link_bpp_limits(struct intel_dp *intel_dp,
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const struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
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int max_link_bpp_x16;
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max_link_bpp_x16 = to_bpp_x16(limits->pipe.max_bpp);
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max_link_bpp_x16 = min(crtc_state->max_link_bpp_x16,
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to_bpp_x16(limits->pipe.max_bpp));
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if (!dsc) {
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max_link_bpp_x16 = rounddown(max_link_bpp_x16, to_bpp_x16(2 * 3));
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@ -13,6 +13,7 @@
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#include "intel_display_types.h"
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#include "intel_fdi.h"
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#include "intel_fdi_regs.h"
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#include "intel_link_bw.h"
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struct intel_fdi_funcs {
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void (*fdi_link_train)(struct intel_crtc *crtc,
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@ -129,13 +130,16 @@ static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
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}
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static int ilk_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
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struct intel_crtc_state *pipe_config)
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struct intel_crtc_state *pipe_config,
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enum pipe *pipe_to_reduce)
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{
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struct drm_i915_private *dev_priv = to_i915(dev);
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struct drm_atomic_state *state = pipe_config->uapi.state;
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struct intel_crtc *other_crtc;
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struct intel_crtc_state *other_crtc_state;
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*pipe_to_reduce = pipe;
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drm_dbg_kms(&dev_priv->drm,
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"checking fdi config on pipe %c, lanes %i\n",
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pipe_name(pipe), pipe_config->fdi_lanes);
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@ -198,6 +202,9 @@ static int ilk_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
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if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
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drm_dbg_kms(&dev_priv->drm,
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"fdi link B uses too many lanes to enable link C\n");
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*pipe_to_reduce = PIPE_B;
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return -EINVAL;
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}
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return 0;
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@ -232,16 +239,42 @@ int intel_fdi_link_freq(struct drm_i915_private *i915,
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return i915->display.fdi.pll_freq;
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}
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/**
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* intel_fdi_compute_pipe_bpp - compute pipe bpp limited by max link bpp
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* @crtc_state: the crtc state
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*
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* Compute the pipe bpp limited by the CRTC's maximum link bpp. Encoders can
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* call this function during state computation in the simple case where the
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* link bpp will always match the pipe bpp. This is the case for all non-DP
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* encoders, while DP encoders will use a link bpp lower than pipe bpp in case
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* of DSC compression.
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*
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* Returns %true in case of success, %false if pipe bpp would need to be
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* reduced below its valid range.
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*/
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bool intel_fdi_compute_pipe_bpp(struct intel_crtc_state *crtc_state)
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{
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int pipe_bpp = min(crtc_state->pipe_bpp,
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to_bpp_int(crtc_state->max_link_bpp_x16));
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pipe_bpp = rounddown(pipe_bpp, 2 * 3);
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if (pipe_bpp < 6 * 3)
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return false;
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crtc_state->pipe_bpp = pipe_bpp;
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return true;
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}
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int ilk_fdi_compute_config(struct intel_crtc *crtc,
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struct intel_crtc_state *pipe_config)
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{
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struct drm_device *dev = crtc->base.dev;
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struct drm_i915_private *i915 = to_i915(dev);
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const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
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int lane, link_bw, fdi_dotclock, ret;
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bool needs_recompute = false;
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int lane, link_bw, fdi_dotclock;
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retry:
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/* FDI is a binary signal running at ~2.7GHz, encoding
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* each output octet as 10 bits. The actual frequency
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* is stored as a divider into a 100MHz clock, and the
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@ -261,25 +294,69 @@ int ilk_fdi_compute_config(struct intel_crtc *crtc,
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intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
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link_bw, &pipe_config->fdi_m_n, false);
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ret = ilk_check_fdi_lanes(dev, crtc->pipe, pipe_config);
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if (ret == -EDEADLK)
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return 0;
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}
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static int intel_fdi_atomic_check_bw(struct intel_atomic_state *state,
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struct intel_crtc *crtc,
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struct intel_crtc_state *pipe_config,
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struct intel_link_bw_limits *limits)
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{
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struct drm_i915_private *i915 = to_i915(crtc->base.dev);
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enum pipe pipe_to_reduce;
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int ret;
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ret = ilk_check_fdi_lanes(&i915->drm, crtc->pipe, pipe_config,
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&pipe_to_reduce);
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if (ret != -EINVAL)
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return ret;
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if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
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pipe_config->pipe_bpp -= 2*3;
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drm_dbg_kms(&i915->drm,
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"fdi link bw constraint, reducing pipe bpp to %i\n",
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pipe_config->pipe_bpp);
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needs_recompute = true;
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pipe_config->bw_constrained = true;
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ret = intel_link_bw_reduce_bpp(state, limits,
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BIT(pipe_to_reduce),
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"FDI link BW");
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goto retry;
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return ret ? : -EAGAIN;
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}
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/**
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* intel_fdi_atomic_check_link - check all modeset FDI link configuration
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* @state: intel atomic state
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* @limits: link BW limits
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*
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* Check the link configuration for all modeset FDI outputs. If the
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* configuration is invalid @limits will be updated if possible to
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* reduce the total BW, after which the configuration for all CRTCs in
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* @state must be recomputed with the updated @limits.
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*
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* Returns:
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* - 0 if the confugration is valid
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* - %-EAGAIN, if the configuration is invalid and @limits got updated
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* with fallback values with which the configuration of all CRTCs
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* in @state must be recomputed
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* - Other negative error, if the configuration is invalid without a
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* fallback possibility, or the check failed for another reason
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*/
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int intel_fdi_atomic_check_link(struct intel_atomic_state *state,
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struct intel_link_bw_limits *limits)
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{
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struct intel_crtc *crtc;
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struct intel_crtc_state *crtc_state;
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int i;
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for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
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int ret;
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if (!crtc_state->has_pch_encoder ||
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!intel_crtc_needs_modeset(crtc_state) ||
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!crtc_state->hw.enable)
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continue;
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ret = intel_fdi_atomic_check_bw(state, crtc, crtc_state, limits);
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if (ret)
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return ret;
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}
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if (needs_recompute)
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return -EAGAIN;
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return ret;
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return 0;
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}
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static void cpt_set_fdi_bc_bifurcation(struct drm_i915_private *dev_priv, bool enable)
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@ -6,16 +6,23 @@
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#ifndef _INTEL_FDI_H_
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#define _INTEL_FDI_H_
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#include <linux/types.h>
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enum pipe;
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struct drm_i915_private;
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struct intel_atomic_state;
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struct intel_crtc;
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struct intel_crtc_state;
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struct intel_encoder;
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struct intel_link_bw_limits;
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int intel_fdi_link_freq(struct drm_i915_private *i915,
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const struct intel_crtc_state *pipe_config);
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bool intel_fdi_compute_pipe_bpp(struct intel_crtc_state *crtc_state);
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int ilk_fdi_compute_config(struct intel_crtc *intel_crtc,
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struct intel_crtc_state *pipe_config);
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int intel_fdi_atomic_check_link(struct intel_atomic_state *state,
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struct intel_link_bw_limits *limits);
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void intel_fdi_normal_train(struct intel_crtc *crtc);
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void ilk_fdi_disable(struct intel_crtc *crtc);
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void ilk_fdi_pll_disable(struct intel_crtc *intel_crtc);
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@ -7,6 +7,7 @@
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#include "intel_atomic.h"
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#include "intel_display_types.h"
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#include "intel_fdi.h"
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#include "intel_link_bw.h"
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/**
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static int check_all_link_config(struct intel_atomic_state *state,
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struct intel_link_bw_limits *limits)
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{
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/* TODO: Check all shared display link configurations like FDI */
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/* TODO: Check additional shared display link configurations like MST */
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int ret;
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ret = intel_fdi_atomic_check_link(state, limits);
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if (ret)
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return ret;
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return 0;
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}
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@ -425,11 +425,18 @@ static int intel_lvds_compute_config(struct intel_encoder *encoder,
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return -EINVAL;
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}
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if (HAS_PCH_SPLIT(i915)) {
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crtc_state->has_pch_encoder = true;
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if (!intel_fdi_compute_pipe_bpp(crtc_state))
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return -EINVAL;
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}
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if (lvds_encoder->a3_power == LVDS_A3_POWER_UP)
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lvds_bpp = 8*3;
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else
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lvds_bpp = 6*3;
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/* TODO: Check crtc_state->max_link_bpp_x16 instead of bw_constrained */
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if (lvds_bpp != crtc_state->pipe_bpp && !crtc_state->bw_constrained) {
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drm_dbg_kms(&i915->drm,
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"forcing display bpp (was %d) to LVDS (%d)\n",
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if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
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return -EINVAL;
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if (HAS_PCH_SPLIT(i915))
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crtc_state->has_pch_encoder = true;
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ret = intel_panel_fitting(crtc_state, conn_state);
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if (ret)
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return ret;
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@ -44,6 +44,7 @@
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#include "intel_crtc.h"
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#include "intel_de.h"
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#include "intel_display_types.h"
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#include "intel_fdi.h"
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#include "intel_fifo_underrun.h"
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#include "intel_gmbus.h"
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#include "intel_hdmi.h"
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struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
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struct drm_display_mode *mode = &pipe_config->hw.mode;
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if (HAS_PCH_SPLIT(to_i915(encoder->base.dev))) {
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pipe_config->has_pch_encoder = true;
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if (!intel_fdi_compute_pipe_bpp(pipe_config))
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return -EINVAL;
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}
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DRM_DEBUG_KMS("forcing bpc to 8 for SDVO\n");
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/* FIXME: Don't increase pipe_bpp */
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pipe_config->pipe_bpp = 8*3;
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pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB;
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pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
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if (HAS_PCH_SPLIT(to_i915(encoder->base.dev)))
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pipe_config->has_pch_encoder = true;
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/*
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* We need to construct preferred input timings based on our
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* output timings. To do that, we have to set the output
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