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perf vendor events intel: Update a spelling in haswell/haswellx

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The spelling of "in-flight" was switched to "inflight".

Signed-off-by: Ian Rogers <irogers@google.com>
Reviewed-by: Kan Liang <kan.liang@linux.intel.com>
Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Edward Baker <edward.baker@intel.com>
Cc: Zhengjun Xing <zhengjun.xing@linux.intel.com>
Link: https://lore.kernel.org/r/20231026003149.3287633-3-irogers@google.com
Signed-off-by: Namhyung Kim <namhyung@kernel.org>
This commit is contained in:
Ian Rogers 2023-10-25 17:31:43 -07:00 committed by Namhyung Kim
parent 8a94d3bfaf
commit 99a8a4c990
2 changed files with 2 additions and 2 deletions
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2
tools/perf/pmu-events/arch/x86/haswell/memory.json
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@ -62,7 +62,7 @@
"BriefDescription": "Counts the number of machine clears due to memory order conflicts.",
"EventCode": "0xC3",
"EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
"PublicDescription": "This event counts the number of memory ordering machine clears detected. Memory ordering machine clears can result from memory address aliasing or snoops from another hardware thread or core to data in-flight in the pipeline. Machine clears can have a significant performance impact if they are happening frequently.",
"PublicDescription": "This event counts the number of memory ordering machine clears detected. Memory ordering machine clears can result from memory address aliasing or snoops from another hardware thread or core to data inflight in the pipeline. Machine clears can have a significant performance impact if they are happening frequently.",
"SampleAfterValue": "100003",
"UMask": "0x2"
},

2
tools/perf/pmu-events/arch/x86/haswellx/memory.json
View file

@ -62,7 +62,7 @@
"BriefDescription": "Counts the number of machine clears due to memory order conflicts.",
"EventCode": "0xC3",
"EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
"PublicDescription": "This event counts the number of memory ordering machine clears detected. Memory ordering machine clears can result from memory address aliasing or snoops from another hardware thread or core to data in-flight in the pipeline. Machine clears can have a significant performance impact if they are happening frequently.",
"PublicDescription": "This event counts the number of memory ordering machine clears detected. Memory ordering machine clears can result from memory address aliasing or snoops from another hardware thread or core to data inflight in the pipeline. Machine clears can have a significant performance impact if they are happening frequently.",
"SampleAfterValue": "100003",
"UMask": "0x2"
},