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drm/amd/pp: Refine the interface exported to display
use void * as function parameter type in order for extension. Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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d4d5eace21
commit
99c5e27d33
8 changed files with 14 additions and 13 deletions
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@ -192,7 +192,6 @@ struct amd_pp_simple_clock_info;
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struct amd_pp_display_configuration;
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struct amd_pp_clock_info;
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struct pp_display_clock_request;
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struct pp_wm_sets_with_clock_ranges_soc15;
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struct pp_clock_levels_with_voltage;
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struct pp_clock_levels_with_latency;
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struct amd_pp_clocks;
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@ -261,7 +260,7 @@ struct amd_pm_funcs {
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enum amd_pp_clock_type type,
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struct pp_clock_levels_with_voltage *clocks);
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int (*set_watermarks_for_clocks_ranges)(void *handle,
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struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges);
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void *clock_ranges);
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int (*display_clock_voltage_request)(void *handle,
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struct pp_display_clock_request *clock);
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int (*get_display_mode_validation_clocks)(void *handle,
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@ -1096,17 +1096,17 @@ static int pp_get_clock_by_type_with_voltage(void *handle,
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}
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static int pp_set_watermarks_for_clocks_ranges(void *handle,
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struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges)
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void *clock_ranges)
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{
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struct pp_hwmgr *hwmgr = handle;
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int ret = 0;
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if (!hwmgr || !hwmgr->pm_en ||!wm_with_clock_ranges)
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if (!hwmgr || !hwmgr->pm_en || !clock_ranges)
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return -EINVAL;
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mutex_lock(&hwmgr->smu_lock);
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ret = phm_set_watermarks_for_clocks_ranges(hwmgr,
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wm_with_clock_ranges);
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clock_ranges);
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mutex_unlock(&hwmgr->smu_lock);
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return ret;
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@ -435,7 +435,7 @@ int phm_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr,
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}
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int phm_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr,
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struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges)
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void *clock_ranges)
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{
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PHM_FUNC_CHECK(hwmgr);
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@ -443,7 +443,7 @@ int phm_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr,
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return -EINVAL;
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return hwmgr->hwmgr_func->set_watermarks_for_clocks_ranges(hwmgr,
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wm_with_clock_ranges);
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clock_ranges);
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}
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int phm_display_clock_voltage_request(struct pp_hwmgr *hwmgr,
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@ -1108,9 +1108,10 @@ static int smu10_read_sensor(struct pp_hwmgr *hwmgr, int idx,
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}
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static int smu10_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr,
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struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges)
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void *clock_ranges)
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{
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struct smu10_hwmgr *data = hwmgr->backend;
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struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges = clock_ranges;
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Watermarks_t *table = &(data->water_marks_table);
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int result = 0;
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@ -4194,9 +4194,10 @@ static int vega10_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr,
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}
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static int vega10_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr,
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struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges)
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void *clock_range)
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{
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struct vega10_hwmgr *data = hwmgr->backend;
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struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges = clock_range;
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Watermarks_t *table = &(data->smc_state_table.water_marks_table);
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int result = 0;
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@ -1781,10 +1781,11 @@ static int vega12_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr,
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}
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static int vega12_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr,
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struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges)
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void *clock_ranges)
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{
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struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
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Watermarks_t *table = &(data->smc_state_table.water_marks_table);
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struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges = clock_ranges;
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uint32_t i;
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if (!data->registry_data.disable_water_mark &&
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@ -455,7 +455,7 @@ extern int phm_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr,
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enum amd_pp_clock_type type,
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struct pp_clock_levels_with_voltage *clocks);
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extern int phm_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr,
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struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges);
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void *clock_ranges);
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extern int phm_display_clock_voltage_request(struct pp_hwmgr *hwmgr,
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struct pp_display_clock_request *clock);
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@ -293,8 +293,7 @@ struct pp_hwmgr_func {
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int (*get_clock_by_type_with_voltage)(struct pp_hwmgr *hwmgr,
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enum amd_pp_clock_type type,
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struct pp_clock_levels_with_voltage *clocks);
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int (*set_watermarks_for_clocks_ranges)(struct pp_hwmgr *hwmgr,
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struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges);
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int (*set_watermarks_for_clocks_ranges)(struct pp_hwmgr *hwmgr, void *clock_ranges);
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int (*display_clock_voltage_request)(struct pp_hwmgr *hwmgr,
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struct pp_display_clock_request *clock);
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int (*get_max_high_clocks)(struct pp_hwmgr *hwmgr, struct amd_pp_simple_clock_info *clocks);
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