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Code Issues Releases Wiki Activity

drm/amd/pp: Refine the interface exported to display

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use void * as function parameter type in order for extension.

Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Rex Zhu 2018-06-22 18:26:52 +08:00 committed by Alex Deucher
parent d4d5eace21
commit 99c5e27d33
8 changed files with 14 additions and 13 deletions
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3
drivers/gpu/drm/amd/include/kgd_pp_interface.h
View file

@ -192,7 +192,6 @@ struct amd_pp_simple_clock_info;
struct amd_pp_display_configuration; struct amd_pp_display_configuration;
struct amd_pp_clock_info; struct amd_pp_clock_info;
struct pp_display_clock_request; struct pp_display_clock_request;
struct pp_wm_sets_with_clock_ranges_soc15;
struct pp_clock_levels_with_voltage; struct pp_clock_levels_with_voltage;
struct pp_clock_levels_with_latency; struct pp_clock_levels_with_latency;
struct amd_pp_clocks; struct amd_pp_clocks;
@ -261,7 +260,7 @@ struct amd_pm_funcs {
enum amd_pp_clock_type type, enum amd_pp_clock_type type,
struct pp_clock_levels_with_voltage *clocks); struct pp_clock_levels_with_voltage *clocks);
int (*set_watermarks_for_clocks_ranges)(void *handle, int (*set_watermarks_for_clocks_ranges)(void *handle,
struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges); void *clock_ranges);
int (*display_clock_voltage_request)(void *handle, int (*display_clock_voltage_request)(void *handle,
struct pp_display_clock_request *clock); struct pp_display_clock_request *clock);
int (*get_display_mode_validation_clocks)(void *handle, int (*get_display_mode_validation_clocks)(void *handle,

6
drivers/gpu/drm/amd/powerplay/amd_powerplay.c
View file

@ -1096,17 +1096,17 @@ static int pp_get_clock_by_type_with_voltage(void *handle,
} }
static int pp_set_watermarks_for_clocks_ranges(void *handle, static int pp_set_watermarks_for_clocks_ranges(void *handle,
struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges) void *clock_ranges)
{ {
struct pp_hwmgr *hwmgr = handle; struct pp_hwmgr *hwmgr = handle;
int ret = 0; int ret = 0;
if (!hwmgr || !hwmgr->pm_en ||!wm_with_clock_ranges) if (!hwmgr || !hwmgr->pm_en || !clock_ranges)
return -EINVAL; return -EINVAL;
mutex_lock(&hwmgr->smu_lock); mutex_lock(&hwmgr->smu_lock);
ret = phm_set_watermarks_for_clocks_ranges(hwmgr, ret = phm_set_watermarks_for_clocks_ranges(hwmgr,
wm_with_clock_ranges); clock_ranges);
mutex_unlock(&hwmgr->smu_lock); mutex_unlock(&hwmgr->smu_lock);
return ret; return ret;

4
drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
View file

@ -435,7 +435,7 @@ int phm_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr,
} }
int phm_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr, int phm_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr,
struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges) void *clock_ranges)
{ {
PHM_FUNC_CHECK(hwmgr); PHM_FUNC_CHECK(hwmgr);
@ -443,7 +443,7 @@ int phm_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr,
return -EINVAL; return -EINVAL;
return hwmgr->hwmgr_func->set_watermarks_for_clocks_ranges(hwmgr, return hwmgr->hwmgr_func->set_watermarks_for_clocks_ranges(hwmgr,
wm_with_clock_ranges); clock_ranges);
} }
int phm_display_clock_voltage_request(struct pp_hwmgr *hwmgr, int phm_display_clock_voltage_request(struct pp_hwmgr *hwmgr,

3
drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
View file

@ -1108,9 +1108,10 @@ static int smu10_read_sensor(struct pp_hwmgr *hwmgr, int idx,
} }
static int smu10_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr, static int smu10_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr,
struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges) void *clock_ranges)
{ {
struct smu10_hwmgr *data = hwmgr->backend; struct smu10_hwmgr *data = hwmgr->backend;
struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges = clock_ranges;
Watermarks_t *table = &(data->water_marks_table); Watermarks_t *table = &(data->water_marks_table);
int result = 0; int result = 0;

3
drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
View file

@ -4194,9 +4194,10 @@ static int vega10_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr,
} }
static int vega10_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr, static int vega10_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr,
struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges) void *clock_range)
{ {
struct vega10_hwmgr *data = hwmgr->backend; struct vega10_hwmgr *data = hwmgr->backend;
struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges = clock_range;
Watermarks_t *table = &(data->smc_state_table.water_marks_table); Watermarks_t *table = &(data->smc_state_table.water_marks_table);
int result = 0; int result = 0;

3
drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
View file

@ -1781,10 +1781,11 @@ static int vega12_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr,
} }
static int vega12_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr, static int vega12_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr,
struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges) void *clock_ranges)
{ {
struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
Watermarks_t *table = &(data->smc_state_table.water_marks_table); Watermarks_t *table = &(data->smc_state_table.water_marks_table);
struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges = clock_ranges;
uint32_t i; uint32_t i;
if (!data->registry_data.disable_water_mark && if (!data->registry_data.disable_water_mark &&

2
drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h
View file

@ -455,7 +455,7 @@ extern int phm_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr,
enum amd_pp_clock_type type, enum amd_pp_clock_type type,
struct pp_clock_levels_with_voltage *clocks); struct pp_clock_levels_with_voltage *clocks);
extern int phm_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr, extern int phm_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr,
struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges); void *clock_ranges);
extern int phm_display_clock_voltage_request(struct pp_hwmgr *hwmgr, extern int phm_display_clock_voltage_request(struct pp_hwmgr *hwmgr,
struct pp_display_clock_request *clock); struct pp_display_clock_request *clock);

3
drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
View file

@ -293,8 +293,7 @@ struct pp_hwmgr_func {
int (*get_clock_by_type_with_voltage)(struct pp_hwmgr *hwmgr, int (*get_clock_by_type_with_voltage)(struct pp_hwmgr *hwmgr,
enum amd_pp_clock_type type, enum amd_pp_clock_type type,
struct pp_clock_levels_with_voltage *clocks); struct pp_clock_levels_with_voltage *clocks);
int (*set_watermarks_for_clocks_ranges)(struct pp_hwmgr *hwmgr, int (*set_watermarks_for_clocks_ranges)(struct pp_hwmgr *hwmgr, void *clock_ranges);
struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges);
int (*display_clock_voltage_request)(struct pp_hwmgr *hwmgr, int (*display_clock_voltage_request)(struct pp_hwmgr *hwmgr,
struct pp_display_clock_request *clock); struct pp_display_clock_request *clock);
int (*get_max_high_clocks)(struct pp_hwmgr *hwmgr, struct amd_pp_simple_clock_info *clocks); int (*get_max_high_clocks)(struct pp_hwmgr *hwmgr, struct amd_pp_simple_clock_info *clocks);