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ARM: arm-soc multiplatform updates for 3.10 

More multiplatform enablement for ARM platforms. The ones converted in
 this branch are:
 - bcm2835
 - cns3xxx
 - sirf
 - nomadik
 - msx
 - spear
 - tegra
 - ux500
 
 We're getting close to having most of them converted!
 
 One of the larger platforms remaining is Samsung Exynos, and there are
 a bunch of supporting patches in this merge window for it. There was a
 patch in this branch to a early version of multiplatform conversion,
 but it ended up being reverted due to need of more bake time. The
 revert commit is part of the branch since it would have required
 rebasing multiple dependent branches and they were stable by then.
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Merge tag 'multiplatform-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC multiplatform updates from Olof Johansson:
 "More multiplatform enablement for ARM platforms.  The ones converted
  in this branch are:

   - bcm2835
   - cns3xxx
   - sirf
   - nomadik
   - msx
   - spear
   - tegra
   - ux500

  We're getting close to having most of them converted!

  One of the larger platforms remaining is Samsung Exynos, and there are
  a bunch of supporting patches in this merge window for it.  There was
  a patch in this branch to a early version of multiplatform conversion,
  but it ended up being reverted due to need of more bake time.  The
  revert commit is part of the branch since it would have required
  rebasing multiple dependent branches and they were stable by then"

* tag 'multiplatform-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (70 commits)
  mmc: sdhci-s3c: Fix operation on non-single image Samsung platforms
  clocksource: nomadik-mtu: fix up clocksource/timer
  Revert "ARM: exynos: enable multiplatform support"
  ARM: SPEAr13xx: Fix typo "ARCH_HAVE_CPUFREQ"
  ARM: exynos: enable multiplatform support
  rtc: s3c: make header file local
  mtd: onenand/samsung: make regs-onenand.h file local
  thermal/exynos: remove unnecessary header inclusions
  mmc: sdhci-s3c: remove platform dependencies
  ARM: samsung: move mfc device definition to s5p-dev-mfc.c
  ARM: exynos: move debug-macro.S to include/debug/
  ARM: exynos: prepare for sparse IRQ
  ARM: exynos: introduce EXYNOS_ATAGS symbol
  ARM: tegra: build assembly files with -march=armv7-a
  ARM: Push selects for TWD/SCU into machine entries
  ARM: ux500: build hotplug.o for ARMv7-a
  ARM: ux500: move to multiplatform
  ARM: ux500: make remaining headers local
  ARM: ux500: make irqs.h local to platform
  ARM: ux500: get rid of <mach/[hardware|db8500-regs].h>
  ...
This commit is contained in:
Linus Torvalds 2013-05-02 09:38:16 -07:00
parent 97b1007a29 2fdfe1c26f
commit 99c6bcf46d
236 changed files with 1832 additions and 2885 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

135
arch/arm/Kconfig
View File

@ -362,37 +362,6 @@ config ARCH_AT91
This enables support for systems based on Atmel
AT91RM9200 and AT91SAM9* processors.
config ARCH_BCM2835
bool "Broadcom BCM2835 family"
select ARCH_REQUIRE_GPIOLIB
select ARM_AMBA
select ARM_ERRATA_411920
select ARM_TIMER_SP804
select CLKDEV_LOOKUP
select CLKSRC_OF
select COMMON_CLK
select CPU_V6
select GENERIC_CLOCKEVENTS
select MULTI_IRQ_HANDLER
select PINCTRL
select PINCTRL_BCM2835
select SPARSE_IRQ
select USE_OF
help
This enables support for the Broadcom BCM2835 SoC. This SoC is
use in the Raspberry Pi, and Roku 2 devices.
config ARCH_CNS3XXX
bool "Cavium Networks CNS3XXX family"
select ARM_GIC
select CPU_V6K
select GENERIC_CLOCKEVENTS
select MIGHT_HAVE_CACHE_L2X0
select MIGHT_HAVE_PCI
select PCI_DOMAINS if PCI
help
Support for Cavium Networks CNS3XXX platform.
config ARCH_CLPS711X
bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
select ARCH_REQUIRE_GPIOLIB
@ -416,21 +385,6 @@ config ARCH_GEMINI
help
Support for the Cortina Systems Gemini family SoCs
config ARCH_SIRF
bool "CSR SiRF"
select ARCH_REQUIRE_GPIOLIB
select AUTO_ZRELADDR
select COMMON_CLK
select GENERIC_CLOCKEVENTS
select GENERIC_IRQ_CHIP
select MIGHT_HAVE_CACHE_L2X0
select NO_IOPORT
select PINCTRL
select PINCTRL_SIRF
select USE_OF
help
Support for CSR SiRFprimaII/Marco/Polo platforms
config ARCH_EBSA110
bool "EBSA-110"
select ARCH_USES_GETTIMEOFFSET
@ -470,23 +424,6 @@ config ARCH_FOOTBRIDGE
Support for systems based on the DC21285 companion chip
("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
config ARCH_MXS
bool "Freescale MXS-based"
select ARCH_REQUIRE_GPIOLIB
select CLKDEV_LOOKUP
select CLKSRC_MMIO
select CLKSRC_OF
select COMMON_CLK
select GENERIC_CLOCKEVENTS
select HAVE_CLK_PREPARE
select MULTI_IRQ_HANDLER
select PINCTRL
select SPARSE_IRQ
select STMP_DEVICE
select USE_OF
help
Support for Freescale MXS-based family of processors
config ARCH_NETX
bool "Hilscher NetX based"
select ARM_VIC
@ -659,25 +596,6 @@ config ARCH_LPC32XX
help
Support for the NXP LPC32XX family of processors
config ARCH_TEGRA
bool "NVIDIA Tegra"
select ARCH_HAS_CPUFREQ
select ARCH_REQUIRE_GPIOLIB
select CLKDEV_LOOKUP
select CLKSRC_MMIO
select CLKSRC_OF
select COMMON_CLK
select GENERIC_CLOCKEVENTS
select HAVE_CLK
select HAVE_SMP
select MIGHT_HAVE_CACHE_L2X0
select SOC_BUS
select SPARSE_IRQ
select USE_OF
help
This enables support for NVIDIA Tegra based systems (Tegra APX,
Tegra 6xx and Tegra 2 series).
config ARCH_PXA
bool "PXA2xx/PXA3xx-based"
depends on MMU
@ -715,6 +633,8 @@ config ARCH_SHMOBILE
bool "Renesas SH-Mobile / R-Mobile"
select CLKDEV_LOOKUP
select GENERIC_CLOCKEVENTS
select HAVE_ARM_SCU if SMP
select HAVE_ARM_TWD if LOCAL_TIMERS
select HAVE_CLK
select HAVE_MACH_CLKDEV
select HAVE_SMP
@ -900,51 +820,6 @@ config ARCH_U300
help
Support for ST-Ericsson U300 series mobile platforms.
config ARCH_U8500
bool "ST-Ericsson U8500 Series"
depends on MMU
select ARCH_HAS_CPUFREQ
select ARCH_REQUIRE_GPIOLIB
select ARM_AMBA
select CLKDEV_LOOKUP
select CPU_V7
select GENERIC_CLOCKEVENTS
select HAVE_SMP
select MIGHT_HAVE_CACHE_L2X0
select SPARSE_IRQ
help
Support for ST-Ericsson's Ux500 architecture
config ARCH_NOMADIK
bool "STMicroelectronics Nomadik"
select ARCH_REQUIRE_GPIOLIB
select ARM_AMBA
select ARM_VIC
select CLKSRC_NOMADIK_MTU
select COMMON_CLK
select CPU_ARM926T
select GENERIC_CLOCKEVENTS
select MIGHT_HAVE_CACHE_L2X0
select USE_OF
select PINCTRL
select PINCTRL_STN8815
select SPARSE_IRQ
help
Support for the Nomadik platform by ST-Ericsson
config PLAT_SPEAR
bool "ST SPEAr"
select ARCH_HAS_CPUFREQ
select ARCH_REQUIRE_GPIOLIB
select ARM_AMBA
select CLKDEV_LOOKUP
select CLKSRC_MMIO
select COMMON_CLK
select GENERIC_CLOCKEVENTS
select HAVE_CLK
help
Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
config ARCH_DAVINCI
bool "TI DaVinci"
select ARCH_HAS_HOLES_MEMORYMODEL
@ -1036,6 +911,8 @@ source "arch/arm/mach-at91/Kconfig"
source "arch/arm/mach-bcm/Kconfig"
source "arch/arm/mach-bcm2835/Kconfig"
source "arch/arm/mach-clps711x/Kconfig"
source "arch/arm/mach-cns3xxx/Kconfig"
@ -1101,7 +978,7 @@ source "arch/arm/plat-samsung/Kconfig"
source "arch/arm/mach-socfpga/Kconfig"
source "arch/arm/plat-spear/Kconfig"
source "arch/arm/mach-spear/Kconfig"
source "arch/arm/mach-s3c24xx/Kconfig"
@ -1528,7 +1405,6 @@ config SMP
depends on GENERIC_CLOCKEVENTS
depends on HAVE_SMP
depends on MMU
select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
select USE_GENERIC_SMP_HELPERS
help
This enables support for systems with more than one CPU. If you have
@ -1653,7 +1529,6 @@ config LOCAL_TIMERS
bool "Use local timer interrupts"
depends on SMP
default y
select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
help
Enable support for local timers on SMP platforms, rather then the
legacy IPI broadcast method. Local timers allows the system

39
arch/arm/Kconfig.debug
View File

@ -89,6 +89,10 @@ choice
bool "Kernel low-level debugging on 9263 and 9g45"
depends on HAVE_AT91_DBGU1
config DEBUG_BCM2835
bool "Kernel low-level debugging on BCM2835 PL011 UART"
depends on ARCH_BCM2835
config DEBUG_CLPS711X_UART1
bool "Kernel low-level debugging messages via UART1"
depends on ARCH_CLPS711X
@ -103,6 +107,13 @@ choice
Say Y here if you want the debug print routines to direct
their output to the second serial port on these devices.
config DEBUG_CNS3XXX
bool "Kernel Kernel low-level debugging on Cavium Networks CNS3xxx"
depends on ARCH_CNS3XXX
help
Say Y here if you want the debug print routines to direct
their output to the CNS3xxx UART0.
config DEBUG_DAVINCI_DA8XX_UART1
bool "Kernel low-level debugging on DaVinci DA8XX using UART1"
depends on ARCH_DAVINCI_DA8XX
@ -298,6 +309,13 @@ choice
Say Y here if you want kernel low-level debugging support
on MVEBU based platforms.
config DEBUG_NOMADIK_UART
bool "Kernel low-level debugging messages via NOMADIK UART"
depends on ARCH_NOMADIK
help
Say Y here if you want kernel low-level debugging support
on NOMADIK based platforms.
config DEBUG_OMAP2PLUS_UART
bool "Kernel low-level debugging messages via OMAP2PLUS UART"
depends on ARCH_OMAP2PLUS
@ -330,6 +348,7 @@ choice
config DEBUG_S3C_UART0
depends on PLAT_SAMSUNG
select DEBUG_EXYNOS_UART if ARCH_EXYNOS
bool "Use S3C UART 0 for low-level debug"
help
Say Y here if you want the debug print routines to direct
@ -341,6 +360,7 @@ choice
config DEBUG_S3C_UART1
depends on PLAT_SAMSUNG
select DEBUG_EXYNOS_UART if ARCH_EXYNOS
bool "Use S3C UART 1 for low-level debug"
help
Say Y here if you want the debug print routines to direct
@ -352,6 +372,7 @@ choice
config DEBUG_S3C_UART2
depends on PLAT_SAMSUNG
select DEBUG_EXYNOS_UART if ARCH_EXYNOS
bool "Use S3C UART 2 for low-level debug"
help
Say Y here if you want the debug print routines to direct
@ -363,6 +384,7 @@ choice
config DEBUG_S3C_UART3
depends on PLAT_SAMSUNG && ARCH_EXYNOS
select DEBUG_EXYNOS_UART
bool "Use S3C UART 3 for low-level debug"
help
Say Y here if you want the debug print routines to direct
@ -414,6 +436,13 @@ choice
Say Y here if you want the debug print routines to direct
their output to the uart1 port on SiRFmarco devices.
config DEBUG_UX500_UART
depends on ARCH_U8500
bool "Use Ux500 UART for low-level debug"
help
Say Y here if you want kernel low-level debugging support
on Ux500 based platforms.
config DEBUG_VEXPRESS_UART0_DETECT
bool "Autodetect UART0 on Versatile Express Cortex-A core tiles"
depends on ARCH_VEXPRESS && CPU_CP15_MMU
@ -485,6 +514,9 @@ choice
endchoice
config DEBUG_EXYNOS_UART
bool
config DEBUG_IMX_UART_PORT
int "i.MX Debug UART Port Selection" if DEBUG_IMX1_UART || \
DEBUG_IMX25_UART || \
@ -580,6 +612,9 @@ endchoice
config DEBUG_LL_INCLUDE
string
default "debug/bcm2835.S" if DEBUG_BCM2835
default "debug/cns3xxx.S" if DEBUG_CNS3XXX
default "debug/exynos.S" if DEBUG_EXYNOS_UART
default "debug/icedcc.S" if DEBUG_ICEDCC
default "debug/imx.S" if DEBUG_IMX1_UART || \
DEBUG_IMX25_UART || \
@ -591,14 +626,18 @@ config DEBUG_LL_INCLUDE
DEBUG_IMX6Q_UART
default "debug/highbank.S" if DEBUG_HIGHBANK_UART
default "debug/mvebu.S" if DEBUG_MVEBU_UART
default "debug/mxs.S" if DEBUG_IMX23_UART || DEBUG_IMX28_UART
default "debug/nomadik.S" if DEBUG_NOMADIK_UART
default "debug/omap2plus.S" if DEBUG_OMAP2PLUS_UART
default "debug/picoxcell.S" if DEBUG_PICOXCELL_UART
default "debug/sirf.S" if DEBUG_SIRFPRIMA2_UART1 || DEBUG_SIRFMARCO_UART1
default "debug/socfpga.S" if DEBUG_SOCFPGA_UART
default "debug/sunxi.S" if DEBUG_SUNXI_UART0 || DEBUG_SUNXI_UART1
default "debug/vexpress.S" if DEBUG_VEXPRESS_UART0_DETECT || \
DEBUG_VEXPRESS_UART0_CA9 || DEBUG_VEXPRESS_UART0_RS1
default "debug/vt8500.S" if DEBUG_VT8500_UART0
default "debug/tegra.S" if DEBUG_TEGRA_UART
default "debug/ux500.S" if DEBUG_UX500_UART
default "debug/zynq.S" if DEBUG_ZYNQ_UART0 || DEBUG_ZYNQ_UART1
default "mach/debug-macro.S"

5
arch/arm/Makefile
View File

@ -190,9 +190,7 @@ machine-$(CONFIG_ARCH_VT8500) += vt8500
machine-$(CONFIG_ARCH_W90X900) += w90x900
machine-$(CONFIG_FOOTBRIDGE) += footbridge
machine-$(CONFIG_ARCH_SOCFPGA) += socfpga
machine-$(CONFIG_ARCH_SPEAR13XX) += spear13xx
machine-$(CONFIG_ARCH_SPEAR3XX) += spear3xx
machine-$(CONFIG_MACH_SPEAR600) += spear6xx
machine-$(CONFIG_PLAT_SPEAR) += spear
machine-$(CONFIG_ARCH_VIRT) += virt
machine-$(CONFIG_ARCH_ZYNQ) += zynq
machine-$(CONFIG_ARCH_SUNXI) += sunxi
@ -206,7 +204,6 @@ plat-$(CONFIG_PLAT_ORION) += orion
plat-$(CONFIG_PLAT_PXA) += pxa
plat-$(CONFIG_PLAT_S3C24XX) += samsung
plat-$(CONFIG_PLAT_S5P) += samsung
plat-$(CONFIG_PLAT_SPEAR) += spear
plat-$(CONFIG_PLAT_VERSATILE) += versatile
ifeq ($(CONFIG_ARCH_EBSA110),y)

2
arch/arm/configs/bcm2835_defconfig
View File

@ -29,6 +29,8 @@ CONFIG_EMBEDDED=y
CONFIG_PROFILING=y
CONFIG_OPROFILE=y
CONFIG_JUMP_LABEL=y
CONFIG_ARCH_MULTI_V6=y
# CONFIG_ARCH_MULTI_V7 is not set
CONFIG_ARCH_BCM2835=y
CONFIG_PREEMPT_VOLUNTARY=y
CONFIG_AEABI=y

3
arch/arm/configs/cns3420vb_defconfig
View File

@ -19,8 +19,11 @@ CONFIG_MODULE_FORCE_UNLOAD=y
CONFIG_MODVERSIONS=y
# CONFIG_BLK_DEV_BSG is not set
CONFIG_IOSCHED_CFQ=m
CONFIG_ARCH_MULTI_V6=y
#CONFIG_ARCH_MULTI_V7 is not set
CONFIG_ARCH_CNS3XXX=y
CONFIG_MACH_CNS3420VB=y
CONFIG_DEBUG_CNS3XXX=y
CONFIG_AEABI=y
CONFIG_ZBOOT_ROM_TEXT=0x0
CONFIG_ZBOOT_ROM_BSS=0x0

23
arch/arm/configs/multi_v7_defconfig
View File

@ -3,13 +3,19 @@ CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_ARCH_MVEBU=y
CONFIG_MACH_ARMADA_370=y
CONFIG_ARCH_SIRF=y
CONFIG_MACH_ARMADA_XP=y
CONFIG_ARCH_HIGHBANK=y
CONFIG_ARCH_SOCFPGA=y
CONFIG_ARCH_SUNXI=y
CONFIG_ARCH_WM8850=y
# CONFIG_ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA is not set
CONFIG_ARCH_ZYNQ=y
CONFIG_ARM_ERRATA_754322=y
CONFIG_PLAT_SPEAR=y
CONFIG_ARCH_SPEAR13XX=y
CONFIG_MACH_SPEAR1310=y
CONFIG_MACH_SPEAR1340=y
CONFIG_SMP=y
CONFIG_ARM_ARCH_TIMER=y
CONFIG_AEABI=y
@ -23,6 +29,7 @@ CONFIG_BLK_DEV_SD=y
CONFIG_ATA=y
CONFIG_SATA_HIGHBANK=y
CONFIG_SATA_MV=y
CONFIG_SATA_AHCI_PLATFORM=y
CONFIG_NETDEVICES=y
CONFIG_NET_CALXEDA_XGMAC=y
CONFIG_SMSC911X=y
@ -31,17 +38,26 @@ CONFIG_SERIO_AMBAKMI=y
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_8250_DW=y
CONFIG_KEYBOARD_SPEAR=y
CONFIG_SERIAL_AMBA_PL011=y
CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
CONFIG_SERIAL_OF_PLATFORM=y
CONFIG_SERIAL_SIRFSOC=y
CONFIG_SERIAL_SIRFSOC_CONSOLE=y
CONFIG_SERIAL_VT8500=y
CONFIG_SERIAL_VT8500_CONSOLE=y
CONFIG_IPMI_HANDLER=y
CONFIG_IPMI_SI=y
CONFIG_I2C=y
CONFIG_I2C_DESIGNWARE_PLATFORM=y
CONFIG_I2C_SIRF=y
CONFIG_SPI=y
CONFIG_SPI_PL022=y
CONFIG_SPI_SIRF=y
CONFIG_GPIO_PL061=y
CONFIG_FB=y
CONFIG_FB_ARMCLCD=y
CONFIG_FB_WM8505=y
CONFIG_FRAMEBUFFER_CONSOLE=y
CONFIG_USB=y
CONFIG_USB_ISP1760_HCD=y
@ -50,11 +66,18 @@ CONFIG_MMC=y
CONFIG_MMC_ARMMMCI=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_PLTFM=y
CONFIG_MMC_SDHCI_SPEAR=y
CONFIG_MMC_WMT=y
CONFIG_EDAC=y
CONFIG_EDAC_MM_EDAC=y
CONFIG_EDAC_HIGHBANK_MC=y
CONFIG_EDAC_HIGHBANK_L2=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_PL031=y
CONFIG_RTC_DRV_VT8500=y
CONFIG_PWM=y
CONFIG_PWM_VT8500=y
CONFIG_DMADEVICES=y
CONFIG_PL330_DMA=y
CONFIG_SIRF_DMA=y
CONFIG_DW_DMAC=y

2
arch/arm/configs/mxs_defconfig
View File

@ -22,8 +22,8 @@ CONFIG_MODVERSIONS=y
CONFIG_BLK_DEV_INTEGRITY=y
# CONFIG_IOSCHED_DEADLINE is not set
# CONFIG_IOSCHED_CFQ is not set
# CONFIG_ARCH_MULTI_V7 is not set
CONFIG_ARCH_MXS=y
CONFIG_MACH_MXS_DT=y
# CONFIG_ARM_THUMB is not set
CONFIG_PREEMPT_VOLUNTARY=y
CONFIG_AEABI=y

42
arch/arm/configs/nhk8815_defconfig
View File

@ -1,11 +1,9 @@
CONFIG_EXPERIMENTAL=y
# CONFIG_LOCALVERSION_AUTO is not set
# CONFIG_SWAP is not set
CONFIG_SYSVIPC=y
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_SYSFS_DEPRECATED_V2=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_EXPERT=y
CONFIG_KALLSYMS_ALL=y
@ -13,6 +11,7 @@ CONFIG_SLAB=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
# CONFIG_BLK_DEV_BSG is not set
# CONFIG_ARCH_MULTI_V7 is not set
CONFIG_ARCH_NOMADIK=y
CONFIG_MACH_NOMADIK_8815NHK=y
CONFIG_PREEMPT=y
@ -20,7 +19,6 @@ CONFIG_AEABI=y
CONFIG_ZBOOT_ROM_TEXT=0x0
CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_FPE_NWFPE=y
CONFIG_PM=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
@ -32,14 +30,10 @@ CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
CONFIG_IP_PNP_BOOTP=y
CONFIG_NET_IPIP=y
CONFIG_NET_IPGRE=y
CONFIG_NET_IPGRE_BROADCAST=y
CONFIG_IP_MROUTE=y
# CONFIG_INET_LRO is not set
# CONFIG_IPV6 is not set
CONFIG_BT=m
CONFIG_BT_L2CAP=m
CONFIG_BT_SCO=m
CONFIG_BT_RFCOMM=m
CONFIG_BT_RFCOMM_TTY=y
CONFIG_BT_BNEP=m
@ -53,14 +47,16 @@ CONFIG_BT_HCIVHCI=m
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_MTD=y
CONFIG_MTD_TESTS=m
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_CHAR=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_NAND=y
CONFIG_MTD_NAND_ECC_SMC=y
CONFIG_MTD_NAND=y
CONFIG_MTD_NAND_FSMC=y
CONFIG_MTD_ONENAND=y
CONFIG_MTD_ONENAND_VERIFY_WRITE=y
CONFIG_MTD_ONENAND_GENERIC=y
CONFIG_PROC_DEVICETREE=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_CRYPTOLOOP=y
CONFIG_BLK_DEV_RAM=y
@ -72,47 +68,48 @@ CONFIG_SCSI_CONSTANTS=y
CONFIG_SCSI_LOGGING=y
CONFIG_SCSI_SCAN_ASYNC=y
CONFIG_NETDEVICES=y
CONFIG_NETCONSOLE=m
CONFIG_TUN=y
CONFIG_NET_ETHERNET=y
CONFIG_SMC91X=y
CONFIG_PPP=m
CONFIG_PPP_ASYNC=m
CONFIG_PPP_SYNC_TTY=m
CONFIG_PPP_DEFLATE=m
CONFIG_PPP_BSDCOMP=m
CONFIG_PPP_DEFLATE=m
CONFIG_PPP_MPPE=m
CONFIG_PPPOE=m
CONFIG_NETCONSOLE=m
CONFIG_PPP_ASYNC=m
CONFIG_PPP_SYNC_TTY=m
# CONFIG_INPUT_MOUSEDEV is not set
CONFIG_INPUT_EVDEV=y
# CONFIG_KEYBOARD_ATKBD is not set
# CONFIG_MOUSE_PS2 is not set
# CONFIG_SERIO is not set
# CONFIG_LEGACY_PTYS is not set
CONFIG_SERIAL_AMBA_PL011=y
CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
# CONFIG_LEGACY_PTYS is not set
# CONFIG_HW_RANDOM is not set
CONFIG_I2C=y
CONFIG_HW_RANDOM=y
CONFIG_HW_RANDOM_NOMADIK=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_GPIO=y
CONFIG_I2C_NOMADIK=y
CONFIG_DEBUG_GPIO=y
CONFIG_PINCTRL_NOMADIK=y
# CONFIG_HWMON is not set
# CONFIG_VGA_CONSOLE is not set
CONFIG_MMC=y
CONFIG_MMC_CLKGATE=y
CONFIG_MMC_ARMMMCI=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_PL031=y
CONFIG_DMADEVICES=y
CONFIG_AMBA_PL08X=y
CONFIG_EXT2_FS=y
CONFIG_EXT3_FS=y
CONFIG_INOTIFY=y
CONFIG_FUSE_FS=y
CONFIG_MSDOS_FS=y
CONFIG_VFAT_FS=y
CONFIG_TMPFS=y
CONFIG_JFFS2_FS=y
CONFIG_NFS_FS=y
CONFIG_NFS_V3=y
CONFIG_NFS_V3_ACL=y
CONFIG_ROOT_NFS=y
CONFIG_SMB_FS=m
CONFIG_CIFS=m
CONFIG_CIFS_WEAK_PW_HASH=y
CONFIG_NLS_CODEPAGE_437=y
@ -120,12 +117,11 @@ CONFIG_NLS_ASCII=y
CONFIG_NLS_ISO8859_1=y
CONFIG_NLS_ISO8859_15=y
# CONFIG_ENABLE_MUST_CHECK is not set
CONFIG_DEBUG_KERNEL=y
CONFIG_DEBUG_FS=y
# CONFIG_SCHED_DEBUG is not set
# CONFIG_DEBUG_PREEMPT is not set
# CONFIG_DEBUG_BUGVERBOSE is not set
CONFIG_DEBUG_INFO=y
# CONFIG_RCU_CPU_STALL_DETECTOR is not set
CONFIG_CRYPTO_MD5=y
CONFIG_CRYPTO_SHA1=y
CONFIG_CRYPTO_DES=y

2
arch/arm/configs/spear3xx_defconfig
View File

@ -6,7 +6,9 @@ CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
CONFIG_MODVERSIONS=y
CONFIG_PARTITION_ADVANCED=y
# CONFIG_ARCH_MULTI_V7 is not set
CONFIG_PLAT_SPEAR=y
CONFIG_ARCH_SPEAR3XX=y
CONFIG_MACH_SPEAR300=y
CONFIG_MACH_SPEAR310=y
CONFIG_MACH_SPEAR320=y

1
arch/arm/configs/spear6xx_defconfig
View File

@ -6,6 +6,7 @@ CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
CONFIG_MODVERSIONS=y
CONFIG_PARTITION_ADVANCED=y
# CONFIG_ARCH_MULTI_V7 is not set
CONFIG_PLAT_SPEAR=y
CONFIG_ARCH_SPEAR6XX=y
CONFIG_BINFMT_MISC=y

3
arch/arm/mach-bcm2835/include/mach/debug-macro.S → arch/arm/include/debug/bcm2835.S
View File

@ -11,7 +11,8 @@
*
*/
#include <mach/bcm2835_soc.h>
#define BCM2835_DEBUG_PHYS 0x20201000
#define BCM2835_DEBUG_VIRT 0xf0201000
.macro addruart, rp, rv, tmp
ldr \rp, =BCM2835_DEBUG_PHYS

0
arch/arm/mach-cns3xxx/include/mach/debug-macro.S → arch/arm/include/debug/cns3xxx.S
View File

12
arch/arm/mach-exynos/include/mach/debug-macro.S → arch/arm/include/debug/exynos.S
View File

@ -1,10 +1,7 @@
/* linux/arch/arm/mach-exynos4/include/mach/debug-macro.S
*
/*
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* Based on arch/arm/mach-s3c6400/include/mach/debug-macro.S
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
@ -12,7 +9,10 @@
/* pull in the relevant register and map files. */
#include <mach/map.h>
#define S3C_ADDR_BASE 0xF6000000
#define S3C_VA_UART S3C_ADDR_BASE + 0x01000000
#define EXYNOS4_PA_UART 0x13800000
#define EXYNOS5_PA_UART 0x12C00000
/* note, for the boot process to work we have to keep the UART
* virtual address aligned to an 1MiB boundary for the L1
@ -36,4 +36,4 @@
#define fifo_full fifo_full_s5pv210
#define fifo_level fifo_level_s5pv210
#include <plat/debug-macro.S>
#include <debug/samsung.S>

0
arch/arm/mach-mxs/include/mach/debug-macro.S → arch/arm/include/debug/mxs.S
View File

0
arch/arm/mach-nomadik/include/mach/debug-macro.S → arch/arm/include/debug/nomadik.S
View File

0
arch/arm/plat-samsung/include/plat/debug-macro.S → arch/arm/include/debug/samsung.S
View File

29
arch/arm/mach-prima2/include/mach/uart.h → arch/arm/include/debug/sirf.S
View File

@ -1,15 +1,11 @@
/*
* arch/arm/mach-prima2/include/mach/uart.h
* arch/arm/mach-prima2/include/mach/debug-macro.S
*
* Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
*
* Licensed under GPLv2 or later.
*/
#ifndef __MACH_PRIMA2_SIRFSOC_UART_H
#define __MACH_PRIMA2_SIRFSOC_UART_H
/* UART-1: used as serial debug port */
#if defined(CONFIG_DEBUG_SIRFPRIMA2_UART1)
#define SIRFSOC_UART1_PA_BASE 0xb0060000
#elif defined(CONFIG_DEBUG_SIRFMARCO_UART1)
@ -17,8 +13,8 @@
#else
#define SIRFSOC_UART1_PA_BASE 0
#endif
#define SIRFSOC_UART1_VA_BASE SIRFSOC_VA(0x060000)
#define SIRFSOC_UART1_SIZE SZ_4K
#define SIRFSOC_UART1_VA_BASE 0xFEC60000
#define SIRFSOC_UART_TXFIFO_STATUS 0x0114
#define SIRFSOC_UART_TXFIFO_DATA 0x0118
@ -26,4 +22,21 @@
#define SIRFSOC_UART1_TXFIFO_FULL (1 << 5)
#define SIRFSOC_UART1_TXFIFO_EMPTY (1 << 6)
#endif
.macro addruart, rp, rv, tmp
ldr \rp, =SIRFSOC_UART1_PA_BASE @ physical
ldr \rv, =SIRFSOC_UART1_VA_BASE @ virtual
.endm
.macro senduart,rd,rx
str \rd, [\rx, #SIRFSOC_UART_TXFIFO_DATA]
.endm
.macro busyuart,rd,rx
.endm
.macro waituart,rd,rx
1001: ldr \rd, [\rx, #SIRFSOC_UART_TXFIFO_STATUS]
tst \rd, #SIRFSOC_UART1_TXFIFO_EMPTY
beq 1001b
.endm

48
arch/arm/include/debug/ux500.S Normal file
View File

@ -0,0 +1,48 @@
/*
* Debugging macro include header
*
* Copyright (C) 2009 ST-Ericsson
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#if CONFIG_UX500_DEBUG_UART > 2
#error Invalid Ux500 debug UART
#endif
/*
* DEBUG_LL only works if only one SOC is built in. We don't use #else below
* in order to get "__UX500_UART redefined" warnings if more than one SOC is
* built, so that there's some hint during the build that something is wrong.
*/
#ifdef CONFIG_UX500_SOC_DB8500
#define U8500_UART0_PHYS_BASE (0x80120000)
#define U8500_UART1_PHYS_BASE (0x80121000)
#define U8500_UART2_PHYS_BASE (0x80007000)
#define U8500_UART0_VIRT_BASE (0xa8120000)
#define U8500_UART1_VIRT_BASE (0xa8121000)
#define U8500_UART2_VIRT_BASE (0xa8007000)
#define __UX500_PHYS_UART(n) U8500_UART##n##_PHYS_BASE
#define __UX500_VIRT_UART(n) U8500_UART##n##_VIRT_BASE
#endif
#if !defined(__UX500_PHYS_UART) || !defined(__UX500_VIRT_UART)
#error Unknown SOC
#endif
#define UX500_PHYS_UART(n) __UX500_PHYS_UART(n)
#define UX500_VIRT_UART(n) __UX500_VIRT_UART(n)
#define UART_PHYS_BASE UX500_PHYS_UART(CONFIG_UX500_DEBUG_UART)
#define UART_VIRT_BASE UX500_VIRT_UART(CONFIG_UX500_DEBUG_UART)
.macro addruart, rp, rv, tmp
ldr \rp, =UART_PHYS_BASE @ no, physical address
ldr \rv, =UART_VIRT_BASE @ yes, virtual address
.endm
#include <asm/hardware/debug-pl01x.S>

15
arch/arm/mach-bcm2835/Kconfig Normal file
View File

@ -0,0 +1,15 @@
config ARCH_BCM2835
bool "Broadcom BCM2835 family" if ARCH_MULTI_V6
select ARCH_REQUIRE_GPIOLIB
select ARM_AMBA
select ARM_ERRATA_411920
select ARM_TIMER_SP804
select CLKDEV_LOOKUP
select CLKSRC_OF
select CPU_V6
select GENERIC_CLOCKEVENTS
select PINCTRL
select PINCTRL_BCM2835
help
This enables support for the Broadcom BCM2835 SoC. This SoC is
use in the Raspberry Pi, and Roku 2 devices.

1
arch/arm/mach-bcm2835/Makefile.boot
View File

@ -1 +0,0 @@
zreladdr-y := 0x00008000

6
arch/arm/mach-bcm2835/bcm2835.c
View File

@ -23,8 +23,6 @@
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <mach/bcm2835_soc.h>
#define PM_RSTC 0x1c
#define PM_RSTS 0x20
#define PM_WDOG 0x24
@ -34,6 +32,10 @@
#define PM_RSTC_WRCFG_FULL_RESET 0x00000020
#define PM_RSTS_HADWRH_SET 0x00000040
#define BCM2835_PERIPH_PHYS 0x20000000
#define BCM2835_PERIPH_VIRT 0xf0000000
#define BCM2835_PERIPH_SIZE SZ_16M
static void __iomem *wdt_regs;
/*

29
arch/arm/mach-bcm2835/include/mach/bcm2835_soc.h
View File

@ -1,29 +0,0 @@
/*
* Copyright (C) 2012 Stephen Warren
*
* Derived from code:
* Copyright (C) 2010 Broadcom
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __MACH_BCM2835_BCM2835_SOC_H__
#define __MACH_BCM2835_BCM2835_SOC_H__
#include <asm/sizes.h>
#define BCM2835_PERIPH_PHYS 0x20000000
#define BCM2835_PERIPH_VIRT 0xf0000000
#define BCM2835_PERIPH_SIZE SZ_16M
#define BCM2835_DEBUG_PHYS 0x20201000
#define BCM2835_DEBUG_VIRT 0xf0201000
#endif

1
arch/arm/mach-bcm2835/include/mach/gpio.h
View File

@ -1 +0,0 @@
/* empty */

26
arch/arm/mach-bcm2835/include/mach/timex.h
View File

@ -1,26 +0,0 @@
/*
* BCM2835 system clock frequency
*
* Copyright (C) 2010 Broadcom
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __ASM_ARCH_TIMEX_H
#define __ASM_ARCH_TIMEX_H
#define CLOCK_TICK_RATE (1000000)
#endif

44
arch/arm/mach-bcm2835/include/mach/uncompress.h
View File

@ -1,44 +0,0 @@
/*
* Copyright (C) 2010 Broadcom
* Copyright (C) 2003 ARM Limited
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/io.h>
#include <linux/amba/serial.h>
#include <mach/bcm2835_soc.h>
#define UART0_BASE BCM2835_DEBUG_PHYS
#define BCM2835_UART_DR IOMEM(UART0_BASE + UART01x_DR)
#define BCM2835_UART_FR IOMEM(UART0_BASE + UART01x_FR)
#define BCM2835_UART_CR IOMEM(UART0_BASE + UART011_CR)
static inline void putc(int c)
{
while (__raw_readl(BCM2835_UART_FR) & UART01x_FR_TXFF)
barrier();
__raw_writel(c, BCM2835_UART_DR);
}
static inline void flush(void)
{
int fr;
do {
fr = __raw_readl(BCM2835_UART_FR);
barrier();
} while ((fr & (UART011_FR_TXFE | UART01x_FR_BUSY)) != UART011_FR_TXFE);
}
#define arch_decomp_setup()

12
arch/arm/mach-cns3xxx/Kconfig
View File

@ -1,8 +1,20 @@
config ARCH_CNS3XXX
bool "Cavium Networks CNS3XXX family" if ARCH_MULTI_V6
select ARM_GIC
select CPU_V6K
select GENERIC_CLOCKEVENTS
select MIGHT_HAVE_CACHE_L2X0
select MIGHT_HAVE_PCI
select PCI_DOMAINS if PCI
help
Support for Cavium Networks CNS3XXX platform.
menu "CNS3XXX platform type"
depends on ARCH_CNS3XXX
config MACH_CNS3420VB
bool "Support for CNS3420 Validation Board"
depends on ATAGS
help
Include support for the Cavium Networks CNS3420 MPCore Platform
Baseboard.

8
arch/arm/mach-cns3xxx/Makefile
View File

@ -1,3 +1,5 @@
obj-$(CONFIG_ARCH_CNS3XXX) += core.o pm.o devices.o
obj-$(CONFIG_PCI) += pcie.o
obj-$(CONFIG_MACH_CNS3420VB) += cns3420vb.o
obj-$(CONFIG_ARCH_CNS3XXX) += cns3xxx.o
cns3xxx-y += core.o pm.o
cns3xxx-$(CONFIG_ATAGS) += devices.o
cns3xxx-$(CONFIG_PCI) += pcie.o
cns3xxx-$(CONFIG_MACH_CNS3420VB) += cns3420vb.o

6
arch/arm/mach-cns3xxx/cns3420vb.c
View File

@ -31,9 +31,8 @@
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/time.h>
#include <mach/cns3xxx.h>
#include <mach/irqs.h>
#include <mach/pm.h>
#include "cns3xxx.h"
#include "pm.h"
#include "core.h"
#include "devices.h"
@ -247,6 +246,7 @@ static void __init cns3420_map_io(void)
MACHINE_START(CNS3420VB, "Cavium Networks CNS3420 Validation Board")
.atag_offset = 0x100,
.nr_irqs = NR_IRQS_CNS3XXX,
.map_io = cns3420_map_io,
.init_irq = cns3xxx_init_irq,
.init_time = cns3xxx_timer_init,

7
arch/arm/mach-cns3xxx/include/mach/cns3xxx.h → arch/arm/mach-cns3xxx/cns3xxx.h
View File

@ -526,6 +526,8 @@ int cns3xxx_cpu_clock(void);
/*
* ARM11 MPCore interrupt sources (primary GIC)
*/
#define IRQ_TC11MP_GIC_START 32
#define IRQ_CNS3XXX_PMU (IRQ_TC11MP_GIC_START + 0)
#define IRQ_CNS3XXX_SDIO (IRQ_TC11MP_GIC_START + 1)
#define IRQ_CNS3XXX_L2CC (IRQ_TC11MP_GIC_START + 2)
@ -597,9 +599,4 @@ int cns3xxx_cpu_clock(void);
#define NR_IRQS_CNS3XXX (IRQ_TC11MP_GIC_START + 64)
#if !defined(NR_IRQS) || (NR_IRQS < NR_IRQS_CNS3XXX)
#undef NR_IRQS
#define NR_IRQS NR_IRQS_CNS3XXX
#endif
#endif /* __MACH_BOARD_CNS3XXX_H */

121
arch/arm/mach-cns3xxx/core.c
View File

@ -13,12 +13,18 @@
#include <linux/clockchips.h>
#include <linux/io.h>
#include <linux/irqchip/arm-gic.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/usb/ehci_pdriver.h>
#include <linux/usb/ohci_pdriver.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/time.h>
#include <asm/mach/irq.h>
#include <asm/hardware/cache-l2x0.h>
#include <mach/cns3xxx.h>
#include "cns3xxx.h"
#include "core.h"
#include "pm.h"
static struct map_desc cns3xxx_io_desc[] __initdata = {
{
@ -256,3 +262,116 @@ void __init cns3xxx_l2x0_init(void)
}
#endif /* CONFIG_CACHE_L2X0 */
static int csn3xxx_usb_power_on(struct platform_device *pdev)
{
/*
* EHCI and OHCI share the same clock and power,
* resetting twice would cause the 1st controller been reset.
* Therefore only do power up at the first up device, and
* power down at the last down device.
*
* Set USB AHB INCR length to 16
*/
if (atomic_inc_return(&usb_pwr_ref) == 1) {
cns3xxx_pwr_power_up(1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_USB);
cns3xxx_pwr_clk_en(1 << PM_CLK_GATE_REG_OFFSET_USB_HOST);
cns3xxx_pwr_soft_rst(1 << PM_SOFT_RST_REG_OFFST_USB_HOST);
__raw_writel((__raw_readl(MISC_CHIP_CONFIG_REG) | (0X2 << 24)),
MISC_CHIP_CONFIG_REG);
}
return 0;
}
static void csn3xxx_usb_power_off(struct platform_device *pdev)
{
/*
* EHCI and OHCI share the same clock and power,
* resetting twice would cause the 1st controller been reset.
* Therefore only do power up at the first up device, and
* power down at the last down device.
*/
if (atomic_dec_return(&usb_pwr_ref) == 0)
cns3xxx_pwr_clk_dis(1 << PM_CLK_GATE_REG_OFFSET_USB_HOST);
}
static struct usb_ehci_pdata cns3xxx_usb_ehci_pdata = {
.power_on = csn3xxx_usb_power_on,
.power_off = csn3xxx_usb_power_off,
};
static struct usb_ohci_pdata cns3xxx_usb_ohci_pdata = {
.num_ports = 1,
.power_on = csn3xxx_usb_power_on,
.power_off = csn3xxx_usb_power_off,
};
static struct of_dev_auxdata cns3xxx_auxdata[] __initconst = {
{ "intel,usb-ehci", CNS3XXX_USB_BASE, "ehci-platform", &cns3xxx_usb_ehci_pdata },
{ "intel,usb-ohci", CNS3XXX_USB_OHCI_BASE, "ohci-platform", &cns3xxx_usb_ohci_pdata },
{ "cavium,cns3420-ahci", CNS3XXX_SATA2_BASE, "ahci", NULL },
{ "cavium,cns3420-sdhci", CNS3XXX_SDIO_BASE, "ahci", NULL },
{},
};
static void __init cns3xxx_init(void)
{
struct device_node *dn;
cns3xxx_l2x0_init();
dn = of_find_compatible_node(NULL, NULL, "cavium,cns3420-ahci");
if (of_device_is_available(dn)) {
u32 tmp;
tmp = __raw_readl(MISC_SATA_POWER_MODE);
tmp |= 0x1 << 16; /* Disable SATA PHY 0 from SLUMBER Mode */
tmp |= 0x1 << 17; /* Disable SATA PHY 1 from SLUMBER Mode */
__raw_writel(tmp, MISC_SATA_POWER_MODE);
/* Enable SATA PHY */
cns3xxx_pwr_power_up(0x1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_SATA_PHY0);
cns3xxx_pwr_power_up(0x1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_SATA_PHY1);
/* Enable SATA Clock */
cns3xxx_pwr_clk_en(0x1 << PM_CLK_GATE_REG_OFFSET_SATA);
/* De-Asscer SATA Reset */
cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(SATA));
}
dn = of_find_compatible_node(NULL, NULL, "cavium,cns3420-sdhci");
if (of_device_is_available(dn)) {
u32 __iomem *gpioa = IOMEM(CNS3XXX_MISC_BASE_VIRT + 0x0014);
u32 gpioa_pins = __raw_readl(gpioa);
/* MMC/SD pins share with GPIOA */
gpioa_pins |= 0x1fff0004;
__raw_writel(gpioa_pins, gpioa);
cns3xxx_pwr_clk_en(CNS3XXX_PWR_CLK_EN(SDIO));
cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(SDIO));
}
pm_power_off = cns3xxx_power_off;
of_platform_populate(NULL, of_default_bus_match_table,
cns3xxx_auxdata, NULL);
}
static const char *cns3xxx_dt_compat[] __initdata = {
"cavium,cns3410",
"cavium,cns3420",
NULL,
};
DT_MACHINE_START(CNS3XXX_DT, "Cavium Networks CNS3xxx")
.dt_compat = cns3xxx_dt_compat,
.nr_irqs = NR_IRQS_CNS3XXX,
.map_io = cns3xxx_map_io,
.init_irq = cns3xxx_init_irq,
.init_time = cns3xxx_timer_init,
.init_machine = cns3xxx_init,
.restart = cns3xxx_restart,
MACHINE_END

5
arch/arm/mach-cns3xxx/devices.c
View File

@ -16,9 +16,8 @@
#include <linux/compiler.h>
#include <linux/dma-mapping.h>
#include <linux/platform_device.h>
#include <mach/cns3xxx.h>
#include <mach/irqs.h>
#include <mach/pm.h>
#include "cns3xxx.h"
#include "pm.h"
#include "core.h"
#include "devices.h"

24
arch/arm/mach-cns3xxx/include/mach/irqs.h
View File

@ -1,24 +0,0 @@
/*
* Copyright 2000 Deep Blue Solutions Ltd.
* Copyright 2003 ARM Limited
* Copyright 2008 Cavium Networks
*
* This file is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, Version 2, as
* published by the Free Software Foundation.
*/
#ifndef __MACH_IRQS_H
#define __MACH_IRQS_H
#define IRQ_LOCALTIMER 29
#define IRQ_LOCALWDOG 30
#define IRQ_TC11MP_GIC_START 32
#include <mach/cns3xxx.h>
#ifndef NR_IRQS
#error "NR_IRQS not defined by the board-specific files"
#endif
#endif

12
arch/arm/mach-cns3xxx/include/mach/timex.h
View File

@ -1,12 +0,0 @@
/*
* Cavium Networks architecture timex specifications
*
* Copyright 2003 ARM Limited
* Copyright 2008 Cavium Networks
*
* This file is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, Version 2, as
* published by the Free Software Foundation.
*/
#define CLOCK_TICK_RATE (50000000 / 16)

53
arch/arm/mach-cns3xxx/include/mach/uncompress.h
View File

@ -1,53 +0,0 @@
/*
* Copyright 2003 ARM Limited
* Copyright 2008 Cavium Networks
*
* This file is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, Version 2, as
* published by the Free Software Foundation.
*/
#include <asm/mach-types.h>
#include <mach/cns3xxx.h>
#define AMBA_UART_DR(base) (*(volatile unsigned char *)((base) + 0x00))
#define AMBA_UART_LCRH(base) (*(volatile unsigned char *)((base) + 0x2c))
#define AMBA_UART_CR(base) (*(volatile unsigned char *)((base) + 0x30))
#define AMBA_UART_FR(base) (*(volatile unsigned char *)((base) + 0x18))
/*
* Return the UART base address
*/
static inline unsigned long get_uart_base(void)
{
if (machine_is_cns3420vb())
return CNS3XXX_UART0_BASE;
else
return 0;
}
/*
* This does not append a newline
*/
static inline void putc(int c)
{
unsigned long base = get_uart_base();
while (AMBA_UART_FR(base) & (1 << 5))
barrier();
AMBA_UART_DR(base) = c;
}
static inline void flush(void)
{
unsigned long base = get_uart_base();
while (AMBA_UART_FR(base) & (1 << 3))
barrier();
}
/*
* nothing to do
*/
#define arch_decomp_setup()

2
arch/arm/mach-cns3xxx/pcie.c
View File

@ -20,7 +20,7 @@
#include <linux/interrupt.h>
#include <linux/ptrace.h>
#include <asm/mach/map.h>
#include <mach/cns3xxx.h>
#include "cns3xxx.h"
#include "core.h"
enum cns3xxx_access_type {

4
arch/arm/mach-cns3xxx/pm.c
View File

@ -11,8 +11,8 @@
#include <linux/io.h>
#include <linux/delay.h>
#include <linux/atomic.h>
#include <mach/cns3xxx.h>
#include <mach/pm.h>
#include "cns3xxx.h"
#include "pm.h"
#include "core.h"
void cns3xxx_pwr_clk_en(unsigned int block)

0
arch/arm/mach-cns3xxx/include/mach/pm.h → arch/arm/mach-cns3xxx/pm.h
View File

17
arch/arm/mach-exynos/Kconfig
View File

@ -14,6 +14,7 @@ menu "SAMSUNG EXYNOS SoCs Support"
config ARCH_EXYNOS4
bool "SAMSUNG EXYNOS4"
default y
select HAVE_ARM_SCU if SMP
select HAVE_SMP
select MIGHT_HAVE_CACHE_L2X0
help
@ -21,6 +22,7 @@ config ARCH_EXYNOS4
config ARCH_EXYNOS5
bool "SAMSUNG EXYNOS5"
select HAVE_ARM_SCU if SMP
select HAVE_SMP
help
Samsung EXYNOS5 (Cortex-A15) SoC based systems
@ -87,6 +89,19 @@ config EXYNOS4_MCT
help
Use MCT (Multi Core Timer) as kernel timers
config EXYNOS_ATAGS
bool "ATAGS based boot for EXYNOS (deprecated)"
depends on !ARCH_MULTIPLATFORM
depends on ATAGS
default y
help
The EXYNOS platform is moving towards being completely probed
through device tree. This enables support for board files using
the traditional ATAGS boot format.
Note that this option is not available for multiplatform builds.
if EXYNOS_ATAGS
config EXYNOS_DEV_DMA
bool
help
@ -391,6 +406,8 @@ config MACH_SMDK4412
Machine support for Samsung SMDK4412
endif
endif
comment "Flattened Device Tree based board for EXYNOS SoCs"
config MACH_EXYNOS4_DT

1
arch/arm/mach-exynos/dev-uart.c
View File

@ -20,6 +20,7 @@
#include <asm/mach/irq.h>
#include <mach/hardware.h>
#include <mach/map.h>
#include <mach/irqs.h>
#include <plat/devs.h>

5
arch/arm/mach-exynos/include/mach/irqs.h
View File

@ -466,7 +466,10 @@
#define IRQ_TIMER_BASE (IRQ_GPIO_END + 64)
/* Set the default NR_IRQS */
#define EXYNOS_NR_IRQS (IRQ_TIMER_BASE + IRQ_TIMER_COUNT)
#define NR_IRQS (IRQ_TIMER_BASE + IRQ_TIMER_COUNT)
#ifndef CONFIG_SPARSE_IRQ
#define NR_IRQS EXYNOS_NR_IRQS
#endif
#endif /* __ASM_ARCH_IRQS_H */

1
arch/arm/mach-exynos/mach-armlex4210.c
View File

@ -25,6 +25,7 @@
#include <plat/regs-srom.h>
#include <plat/sdhci.h>
#include <mach/irqs.h>
#include <mach/map.h>
#include "common.h"

1
arch/arm/mach-exynos/mach-nuri.c
View File

@ -53,6 +53,7 @@
#include <plat/fimc-core.h>
#include <plat/camport.h>
#include <mach/irqs.h>
#include <mach/map.h>
#include "common.h"

1
arch/arm/mach-exynos/mach-origen.c
View File

@ -46,6 +46,7 @@
#include <plat/hdmi.h>
#include <mach/map.h>
#include <mach/irqs.h>
#include <drm/exynos_drm.h>
#include "common.h"

1
arch/arm/mach-exynos/mach-smdk4x12.c
View File

@ -39,6 +39,7 @@
#include <plat/regs-serial.h>
#include <plat/sdhci.h>
#include <mach/irqs.h>
#include <mach/map.h>
#include <drm/exynos_drm.h>

1
arch/arm/mach-exynos/mach-smdkv310.c
View File

@ -43,6 +43,7 @@
#include <plat/clock.h>
#include <plat/hdmi.h>
#include <mach/irqs.h>
#include <mach/map.h>
#include <drm/exynos_drm.h>

2
arch/arm/mach-exynos/setup-sdhci-gpio.c
View File

@ -19,8 +19,8 @@
#include <linux/mmc/host.h>
#include <linux/mmc/card.h>
#include <mach/gpio.h>
#include <plat/gpio-cfg.h>
#include <plat/regs-sdhci.h>
#include <plat/sdhci.h>
void exynos4_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width)

1
arch/arm/mach-highbank/Kconfig
View File

@ -12,6 +12,7 @@ config ARCH_HIGHBANK
select CPU_V7
select GENERIC_CLOCKEVENTS
select HAVE_ARM_SCU
select HAVE_ARM_TWD if LOCAL_TIMERS
select HAVE_SMP
select MAILBOX
select PL320_MBOX

3
arch/arm/mach-imx/Kconfig
View File

@ -795,7 +795,8 @@ config SOC_IMX6Q
select ARM_GIC
select COMMON_CLK
select CPU_V7
select HAVE_ARM_SCU
select HAVE_ARM_SCU if SMP
select HAVE_ARM_TWD if LOCAL_TIMERS
select HAVE_CAN_FLEXCAN if CAN
select HAVE_IMX_GPC
select HAVE_IMX_MMDC

7
arch/arm/mach-msm/Kconfig
View File

@ -44,10 +44,10 @@ endchoice
config ARCH_MSM8X60
bool "MSM8X60"
select ARCH_MSM_SCORPIONMP
select ARM_GIC
select CPU_V7
select GPIO_MSM_V2
select HAVE_SMP
select MSM_GPIOMUX
select MSM_SCM if SMP
select MSM_V2_TLMM
@ -55,9 +55,9 @@ config ARCH_MSM8X60
config ARCH_MSM8960
bool "MSM8960"
select ARCH_MSM_SCORPIONMP
select ARM_GIC
select CPU_V7
select HAVE_SMP
select MSM_GPIOMUX
select MSM_SCM if SMP
select MSM_V2_TLMM
@ -68,9 +68,6 @@ config MSM_HAS_DEBUG_UART_HS
config MSM_SOC_REV_A
bool
config ARCH_MSM_SCORPIONMP
bool
select HAVE_SMP
config ARCH_MSM_ARM11
bool

22
arch/arm/mach-mxs/Kconfig
View File

@ -1,5 +1,3 @@
if ARCH_MXS
config SOC_IMX23
bool
select ARM_AMBA
@ -17,14 +15,18 @@ config SOC_IMX28
select HAVE_PWM
select PINCTRL_IMX28
comment "MXS platforms:"
config MACH_MXS_DT
bool "Support MXS platforms from device tree"
config ARCH_MXS
bool "Freescale MXS (i.MX23, i.MX28) support"
depends on ARCH_MULTI_V5
select ARCH_REQUIRE_GPIOLIB
select CLKDEV_LOOKUP
select CLKSRC_MMIO
select CLKSRC_OF
select GENERIC_CLOCKEVENTS
select HAVE_CLK_PREPARE
select PINCTRL
select SOC_IMX23
select SOC_IMX28
select STMP_DEVICE
help
Include support for Freescale MXS platforms(i.MX23 and i.MX28)
using the device tree for discovery
endif
Support for Freescale MXS-based family of processors

2
arch/arm/mach-mxs/Makefile
View File

@ -1,2 +1,2 @@
obj-$(CONFIG_PM) += pm.o
obj-$(CONFIG_MACH_MXS_DT) += mach-mxs.o
obj-$(CONFIG_ARCH_MXS) += mach-mxs.o

1
arch/arm/mach-mxs/Makefile.boot
View File

@ -1 +0,0 @@
zreladdr-y += 0x40008000

21
arch/arm/mach-mxs/include/mach/timex.h
View File

@ -1,21 +0,0 @@
/*
* Copyright (C) 1999 ARM Limited
* Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __MACH_MXS_TIMEX_H__
#define __MACH_MXS_TIMEX_H__
#define CLOCK_TICK_RATE 32000 /* 32K */
#endif /* __MACH_MXS_TIMEX_H__ */

76
arch/arm/mach-mxs/include/mach/uncompress.h
View File

@ -1,76 +0,0 @@
/*
* arch/arm/mach-mxs/include/mach/uncompress.h
*
* Copyright (C) 1999 ARM Limited
* Copyright (C) Shane Nay (shane@minirl.com)
* Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __MACH_MXS_UNCOMPRESS_H__
#define __MACH_MXS_UNCOMPRESS_H__
unsigned long mxs_duart_base;
#define MXS_DUART(x) (*(volatile unsigned long *)(mxs_duart_base + (x)))
#define MXS_DUART_DR 0x00
#define MXS_DUART_FR 0x18
#define MXS_DUART_FR_TXFE (1 << 7)
#define MXS_DUART_CR 0x30
#define MXS_DUART_CR_UARTEN (1 << 0)
/*
* The following code assumes the serial port has already been
* initialized by the bootloader. If it's not, the output is
* simply discarded.
*/
static void putc(int ch)
{
if (!mxs_duart_base)
return;
if (!(MXS_DUART(MXS_DUART_CR) & MXS_DUART_CR_UARTEN))
return;
while (!(MXS_DUART(MXS_DUART_FR) & MXS_DUART_FR_TXFE))
barrier();
MXS_DUART(MXS_DUART_DR) = ch;
}
static inline void flush(void)
{
}
#define MX23_DUART_BASE_ADDR 0x80070000
#define MX28_DUART_BASE_ADDR 0x80074000
#define MXS_DIGCTL_CHIPID 0x8001c310
static inline void __arch_decomp_setup(unsigned long arch_id)
{
u16 chipid = (*(volatile unsigned long *) MXS_DIGCTL_CHIPID) >> 16;
switch (chipid) {
case 0x3780:
mxs_duart_base = MX23_DUART_BASE_ADDR;
break;
case 0x2800:
mxs_duart_base = MX28_DUART_BASE_ADDR;
break;
default:
break;
}
}
#define arch_decomp_setup() __arch_decomp_setup(arch_id)
#endif /* __MACH_MXS_UNCOMPRESS_H__ */

3
arch/arm/mach-mxs/mach-mxs.c
View File

@ -32,6 +32,8 @@
#include <asm/mach/time.h>
#include <asm/system_misc.h>
#include "pm.h"
/* MXS DIGCTL SAIF CLKMUX */
#define MXS_DIGCTL_SAIF_CLKMUX_DIRECT 0x0
#define MXS_DIGCTL_SAIF_CLKMUX_CROSSINPUT 0x1
@ -607,6 +609,7 @@ DT_MACHINE_START(MXS, "Freescale MXS (Device Tree)")
.handle_irq = icoll_handle_irq,
.init_time = mxs_timer_init,
.init_machine = mxs_machine_init,
.init_late = mxs_pm_init,
.dt_compat = mxs_dt_compat,
.restart = mxs_restart,
MACHINE_END

4
arch/arm/mach-mxs/pm.c
View File

@ -34,9 +34,7 @@ static struct platform_suspend_ops mxs_suspend_ops = {
.valid = suspend_valid_only_mem,
};
static int __init mxs_pm_init(void)
void __init mxs_pm_init(void)
{
suspend_set_ops(&mxs_suspend_ops);
return 0;
}
device_initcall(mxs_pm_init);

14
arch/arm/mach-mxs/pm.h Normal file
View File

@ -0,0 +1,14 @@
/*
* Copyright (C) 2013 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ARCH_MXS_PM_H
#define __ARCH_MXS_PM_H
void mxs_pm_init(void);
#endif

25
arch/arm/mach-nomadik/Kconfig
View File

@ -1,5 +1,24 @@
if ARCH_NOMADIK
config ARCH_NOMADIK
bool "ST-Ericsson Nomadik"
depends on ARCH_MULTI_V5
select ARCH_REQUIRE_GPIOLIB
select ARM_AMBA
select ARM_VIC
select CLKSRC_NOMADIK_MTU
select CLKSRC_NOMADIK_MTU_SCHED_CLOCK
select COMMON_CLK
select CPU_ARM926T
select GENERIC_CLOCKEVENTS
select MIGHT_HAVE_CACHE_L2X0
select PINCTRL
select PINCTRL_NOMADIK
select PINCTRL_STN8815
select SPARSE_IRQ
select USE_OF
help
Support for the Nomadik platform by ST-Ericsson
if ARCH_NOMADIK
menu "Nomadik boards"
config MACH_NOMADIK_8815NHK
@ -9,8 +28,8 @@ config MACH_NOMADIK_8815NHK
select I2C_ALGOBIT
endmenu
endif
config NOMADIK_8815
depends on ARCH_NOMADIK
bool
endif

4
arch/arm/mach-nomadik/Makefile.boot
View File

@ -1,4 +0,0 @@
zreladdr-y += 0x00008000
params_phys-y := 0x00000100
initrd_phys-y := 0x00800000

1
arch/arm/mach-nomadik/cpu-8815.c
View File

@ -38,7 +38,6 @@
#include <linux/gpio.h>
#include <linux/amba/mmci.h>
#include <mach/irqs.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/time.h>

79
arch/arm/mach-nomadik/include/mach/irqs.h
View File

@ -1,79 +0,0 @@
/*
* mach-nomadik/include/mach/irqs.h
*
* Copyright (C) ST Microelectronics
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __ASM_ARCH_IRQS_H
#define __ASM_ARCH_IRQS_H
#define IRQ_VIC_START 32 /* first VIC interrupt is 1 */
/*
* Interrupt numbers generic for all Nomadik Chip cuts
*/
#define IRQ_WATCHDOG (IRQ_VIC_START+0)
#define IRQ_SOFTINT (IRQ_VIC_START+1)
#define IRQ_CRYPTO (IRQ_VIC_START+2)
#define IRQ_OWM (IRQ_VIC_START+3)
#define IRQ_MTU0 (IRQ_VIC_START+4)
#define IRQ_MTU1 (IRQ_VIC_START+5)
#define IRQ_GPIO0 (IRQ_VIC_START+6)
#define IRQ_GPIO1 (IRQ_VIC_START+7)
#define IRQ_GPIO2 (IRQ_VIC_START+8)
#define IRQ_GPIO3 (IRQ_VIC_START+9)
#define IRQ_RTC_RTT (IRQ_VIC_START+10)
#define IRQ_SSP (IRQ_VIC_START+11)
#define IRQ_UART0 (IRQ_VIC_START+12)
#define IRQ_DMA1 (IRQ_VIC_START+13)
#define IRQ_CLCD_MDIF (IRQ_VIC_START+14)
#define IRQ_DMA0 (IRQ_VIC_START+15)
#define IRQ_PWRFAIL (IRQ_VIC_START+16)
#define IRQ_UART1 (IRQ_VIC_START+17)
#define IRQ_FIRDA (IRQ_VIC_START+18)
#define IRQ_MSP0 (IRQ_VIC_START+19)
#define IRQ_I2C0 (IRQ_VIC_START+20)
#define IRQ_I2C1 (IRQ_VIC_START+21)
#define IRQ_SDMMC (IRQ_VIC_START+22)
#define IRQ_USBOTG (IRQ_VIC_START+23)
#define IRQ_SVA_IT0 (IRQ_VIC_START+24)
#define IRQ_SVA_IT1 (IRQ_VIC_START+25)
#define IRQ_SAA_IT0 (IRQ_VIC_START+26)
#define IRQ_SAA_IT1 (IRQ_VIC_START+27)
#define IRQ_UART2 (IRQ_VIC_START+28)
#define IRQ_MSP2 (IRQ_VIC_START+29)
#define IRQ_L2CC (IRQ_VIC_START+30)
#define IRQ_HPI (IRQ_VIC_START+31)
#define IRQ_SKE (IRQ_VIC_START+32)
#define IRQ_KP (IRQ_VIC_START+33)
#define IRQ_MEMST (IRQ_VIC_START+34)
#define IRQ_SGA_IT (IRQ_VIC_START+35)
#define IRQ_USBM (IRQ_VIC_START+36)
#define IRQ_MSP1 (IRQ_VIC_START+37)
#define NOMADIK_GPIO_OFFSET (IRQ_VIC_START+64)
/* After chip-specific IRQ numbers we have the GPIO ones */
#define NOMADIK_NR_GPIO 128 /* last 4 not wired to pins */
#define NOMADIK_GPIO_TO_IRQ(gpio) ((gpio) + NOMADIK_GPIO_OFFSET)
#define NOMADIK_IRQ_TO_GPIO(irq) ((irq) - NOMADIK_GPIO_OFFSET)
#define NOMADIK_NR_IRQS NOMADIK_GPIO_TO_IRQ(NOMADIK_NR_GPIO)
/* Following two are used by entry_macro.S, to access our dual-vic */
#define VIC_REG_IRQSR0 0
#define VIC_REG_IRQSR1 0x20
#endif /* __ASM_ARCH_IRQS_H */

6
arch/arm/mach-nomadik/include/mach/timex.h
View File

@ -1,6 +0,0 @@
#ifndef __ASM_ARCH_TIMEX_H
#define __ASM_ARCH_TIMEX_H
#define CLOCK_TICK_RATE 2400000
#endif

60
arch/arm/mach-nomadik/include/mach/uncompress.h
View File

@ -1,60 +0,0 @@
/*
* Copyright (C) 2008 STMicroelectronics
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __ASM_ARCH_UNCOMPRESS_H
#define __ASM_ARCH_UNCOMPRESS_H
#include <asm/setup.h>
#include <asm/io.h>
/* we need the constants in amba/serial.h, but it refers to amba_device */
struct amba_device;
#include <linux/amba/serial.h>
#define NOMADIK_UART_DR (void __iomem *)0x101FB000
#define NOMADIK_UART_LCRH (void __iomem *)0x101FB02c
#define NOMADIK_UART_CR (void __iomem *)0x101FB030
#define NOMADIK_UART_FR (void __iomem *)0x101FB018
static void putc(const char c)
{
/* Do nothing if the UART is not enabled. */
if (!(readb(NOMADIK_UART_CR) & UART01x_CR_UARTEN))
return;
if (c == '\n')
putc('\r');
while (readb(NOMADIK_UART_FR) & UART01x_FR_TXFF)
barrier();
writeb(c, NOMADIK_UART_DR);
}
static void flush(void)
{
if (!(readb(NOMADIK_UART_CR) & UART01x_CR_UARTEN))
return;
while (readb(NOMADIK_UART_FR) & UART01x_FR_BUSY)
barrier();
}
static inline void arch_decomp_setup(void)
{
}
#endif /* __ASM_ARCH_UNCOMPRESS_H */

2
arch/arm/mach-omap2/Kconfig
View File

@ -91,6 +91,8 @@ config ARCH_OMAP4
select ARM_GIC
select CACHE_L2X0
select CPU_V7
select HAVE_ARM_SCU if SMP
select HAVE_ARM_TWD if LOCAL_TIMERS
select HAVE_SMP
select LOCAL_TIMERS if SMP
select OMAP_INTERCONNECT

13
arch/arm/mach-prima2/Kconfig
View File

@ -1,3 +1,15 @@
config ARCH_SIRF
bool "CSR SiRF" if ARCH_MULTI_V7
select ARCH_REQUIRE_GPIOLIB
select GENERIC_CLOCKEVENTS
select GENERIC_IRQ_CHIP
select MIGHT_HAVE_CACHE_L2X0
select NO_IOPORT
select PINCTRL
select PINCTRL_SIRF
help
Support for CSR SiRFprimaII/Marco/Polo platforms
if ARCH_SIRF
menu "CSR SiRF atlas6/primaII/Marco/Polo Specific Features"
@ -24,6 +36,7 @@ config ARCH_MARCO
default y
select ARM_GIC
select CPU_V7
select HAVE_ARM_SCU if SMP
select HAVE_SMP
select SMP_ON_UP
help

5
arch/arm/mach-prima2/Makefile
View File

@ -4,8 +4,7 @@ obj-y += rtciobrg.o
obj-$(CONFIG_DEBUG_LL) += lluart.o
obj-$(CONFIG_CACHE_L2X0) += l2x0.o
obj-$(CONFIG_SUSPEND) += pm.o sleep.o
obj-$(CONFIG_SIRF_IRQ) += irq.o
obj-$(CONFIG_SMP) += platsmp.o headsmp.o
obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
obj-$(CONFIG_ARCH_PRIMA2) += timer-prima2.o
obj-$(CONFIG_ARCH_MARCO) += timer-marco.o
CFLAGS_hotplug.o += -march=armv7-a

26
arch/arm/mach-prima2/common.c
View File

@ -6,6 +6,7 @@
* Licensed under GPLv2 or later.
*/
#include <linux/clocksource.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/irqchip.h>
@ -31,6 +32,13 @@ void __init sirfsoc_init_late(void)
sirfsoc_pm_init();
}
static __init void sirfsoc_init_time(void)
{
/* initialize clocking early, we want to set the OS timer */
sirfsoc_of_clk_init();
clocksource_of_init();
}
static __init void sirfsoc_map_io(void)
{
sirfsoc_map_lluart();
@ -45,12 +53,10 @@ static const char *atlas6_dt_match[] __initdata = {
DT_MACHINE_START(ATLAS6_DT, "Generic ATLAS6 (Flattened Device Tree)")
/* Maintainer: Barry Song <baohua.song@csr.com> */
.nr_irqs = 128,
.map_io = sirfsoc_map_io,
.init_irq = sirfsoc_of_irq_init,
.init_time = sirfsoc_prima2_timer_init,
#ifdef CONFIG_MULTI_IRQ_HANDLER
.handle_irq = sirfsoc_handle_irq,
#endif
.init_irq = irqchip_init,
.init_time = sirfsoc_init_time,
.init_machine = sirfsoc_mach_init,
.init_late = sirfsoc_init_late,
.dt_compat = atlas6_dt_match,
@ -66,12 +72,10 @@ static const char *prima2_dt_match[] __initdata = {
DT_MACHINE_START(PRIMA2_DT, "Generic PRIMA2 (Flattened Device Tree)")
/* Maintainer: Barry Song <baohua.song@csr.com> */
.nr_irqs = 128,
.map_io = sirfsoc_map_io,
.init_irq = sirfsoc_of_irq_init,
.init_time = sirfsoc_prima2_timer_init,
#ifdef CONFIG_MULTI_IRQ_HANDLER
.handle_irq = sirfsoc_handle_irq,
#endif
.init_irq = irqchip_init,
.init_time = sirfsoc_init_time,
.dma_zone_size = SZ_256M,
.init_machine = sirfsoc_mach_init,
.init_late = sirfsoc_init_late,
@ -91,7 +95,7 @@ DT_MACHINE_START(MARCO_DT, "Generic MARCO (Flattened Device Tree)")
.smp = smp_ops(sirfsoc_smp_ops),
.map_io = sirfsoc_map_io,
.init_irq = irqchip_init,
.init_time = sirfsoc_marco_timer_init,
.init_time = sirfsoc_init_time,
.init_machine = sirfsoc_mach_init,
.init_late = sirfsoc_init_late,
.dt_compat = marco_dt_match,

4
arch/arm/mach-prima2/common.h
View File

@ -13,8 +13,8 @@
#include <asm/mach/time.h>
#include <asm/exception.h>
extern void sirfsoc_prima2_timer_init(void);
extern void sirfsoc_marco_timer_init(void);
#define SIRFSOC_VA_BASE _AC(0xFEC00000, UL)
#define SIRFSOC_VA(x) (SIRFSOC_VA_BASE + ((x) & 0x00FFF000))
extern struct smp_operations sirfsoc_smp_ops;
extern void sirfsoc_secondary_startup(void);

15
arch/arm/mach-prima2/include/mach/clkdev.h
View File

@ -1,15 +0,0 @@
/*
* arch/arm/mach-prima2/include/mach/clkdev.h
*
* Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
*
* Licensed under GPLv2 or later.
*/
#ifndef __MACH_CLKDEV_H
#define __MACH_CLKDEV_H
#define __clk_get(clk) ({ 1; })
#define __clk_put(clk) do { } while (0)
#endif

29
arch/arm/mach-prima2/include/mach/debug-macro.S
View File

@ -1,29 +0,0 @@
/*
* arch/arm/mach-prima2/include/mach/debug-macro.S
*
* Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
*
* Licensed under GPLv2 or later.
*/
#include <mach/hardware.h>
#include <mach/uart.h>
.macro addruart, rp, rv, tmp
ldr \rp, =SIRFSOC_UART1_PA_BASE @ physical
ldr \rv, =SIRFSOC_UART1_VA_BASE @ virtual
.endm
.macro senduart,rd,rx
str \rd, [\rx, #SIRFSOC_UART_TXFIFO_DATA]
.endm
.macro busyuart,rd,rx
.endm
.macro waituart,rd,rx
1001: ldr \rd, [\rx, #SIRFSOC_UART_TXFIFO_STATUS]
tst \rd, #SIRFSOC_UART1_TXFIFO_EMPTY
beq 1001b
.endm

22
arch/arm/mach-prima2/include/mach/entry-macro.S
View File

@ -1,22 +0,0 @@
/*
* arch/arm/mach-prima2/include/mach/entry-macro.S
*
* Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
*
* Licensed under GPLv2 or later.
*/
#include <mach/hardware.h>
#define SIRFSOC_INT_ID 0x38
.macro get_irqnr_preamble, base, tmp
ldr \base, =sirfsoc_intc_base
ldr \base, [\base]
.endm
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
ldr \irqnr, [\base, #SIRFSOC_INT_ID] @ Get the highest priority irq
cmp \irqnr, #0x40 @ the irq num can't be larger than 0x3f
movges \irqnr, #0
.endm

15
arch/arm/mach-prima2/include/mach/hardware.h
View File

@ -1,15 +0,0 @@
/*
* arch/arm/mach-prima2/include/mach/hardware.h
*
* Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
*
* Licensed under GPLv2 or later.
*/
#ifndef __MACH_HARDWARE_H__
#define __MACH_HARDWARE_H__
#include <asm/sizes.h>
#include <mach/map.h>
#endif

17
arch/arm/mach-prima2/include/mach/irqs.h
View File

@ -1,17 +0,0 @@
/*
* arch/arm/mach-prima2/include/mach/irqs.h
*
* Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
*
* Licensed under GPLv2 or later.
*/
#ifndef __ASM_ARCH_IRQS_H
#define __ASM_ARCH_IRQS_H
#define SIRFSOC_INTENAL_IRQ_START 0
#define SIRFSOC_INTENAL_IRQ_END 127
#define SIRFSOC_GPIO_IRQ_START (SIRFSOC_INTENAL_IRQ_END + 1)
#define NR_IRQS 288
#endif

18
arch/arm/mach-prima2/include/mach/map.h
View File

@ -1,18 +0,0 @@
/*
* memory & I/O static mapping definitions for CSR SiRFprimaII
*
* Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
*
* Licensed under GPLv2 or later.
*/
#ifndef __MACH_PRIMA2_MAP_H__
#define __MACH_PRIMA2_MAP_H__
#include <linux/const.h>
#define SIRFSOC_VA_BASE _AC(0xFEC00000, UL)
#define SIRFSOC_VA(x) (SIRFSOC_VA_BASE + ((x) & 0x00FFF000))
#endif

14
arch/arm/mach-prima2/include/mach/timex.h
View File

@ -1,14 +0,0 @@
/*
* arch/arm/mach-prima2/include/mach/timex.h
*
* Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
*
* Licensed under GPLv2 or later.
*/
#ifndef __MACH_TIMEX_H__
#define __MACH_TIMEX_H__
#define CLOCK_TICK_RATE 1000000
#endif

41
arch/arm/mach-prima2/include/mach/uncompress.h
View File

@ -1,41 +0,0 @@
/*
* arch/arm/mach-prima2/include/mach/uncompress.h
*
* Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
*
* Licensed under GPLv2 or later.
*/
#ifndef __ASM_ARCH_UNCOMPRESS_H
#define __ASM_ARCH_UNCOMPRESS_H
#include <linux/io.h>
#include <mach/hardware.h>
#include <mach/uart.h>
void arch_decomp_setup(void)
{
}
static __inline__ void putc(char c)
{
/*
* during kernel decompression, all mappings are flat:
* virt_addr == phys_addr
*/
if (!SIRFSOC_UART1_PA_BASE)
return;
while (__raw_readl((void __iomem *)SIRFSOC_UART1_PA_BASE + SIRFSOC_UART_TXFIFO_STATUS)
& SIRFSOC_UART1_TXFIFO_FULL)
barrier();
__raw_writel(c, (void __iomem *)SIRFSOC_UART1_PA_BASE + SIRFSOC_UART_TXFIFO_DATA);
}
static inline void flush(void)
{
}
#endif

129
arch/arm/mach-prima2/irq.c
View File

@ -1,129 +0,0 @@
/*
* interrupt controller support for CSR SiRFprimaII
*
* Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
*
* Licensed under GPLv2 or later.
*/
#include <linux/init.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/irqdomain.h>
#include <linux/syscore_ops.h>
#include <asm/mach/irq.h>
#include <asm/exception.h>
#include <mach/hardware.h>
#define SIRFSOC_INT_RISC_MASK0 0x0018
#define SIRFSOC_INT_RISC_MASK1 0x001C
#define SIRFSOC_INT_RISC_LEVEL0 0x0020
#define SIRFSOC_INT_RISC_LEVEL1 0x0024
#define SIRFSOC_INIT_IRQ_ID 0x0038
void __iomem *sirfsoc_intc_base;
static __init void
sirfsoc_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num)
{
struct irq_chip_generic *gc;
struct irq_chip_type *ct;
gc = irq_alloc_generic_chip("SIRFINTC", 1, irq_start, base, handle_level_irq);
ct = gc->chip_types;
ct->chip.irq_mask = irq_gc_mask_clr_bit;
ct->chip.irq_unmask = irq_gc_mask_set_bit;
ct->regs.mask = SIRFSOC_INT_RISC_MASK0;
irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE, IRQ_NOREQUEST, 0);
}
static __init void sirfsoc_irq_init(void)
{
sirfsoc_alloc_gc(sirfsoc_intc_base, 0, 32);
sirfsoc_alloc_gc(sirfsoc_intc_base + 4, 32,
SIRFSOC_INTENAL_IRQ_END + 1 - 32);
writel_relaxed(0, sirfsoc_intc_base + SIRFSOC_INT_RISC_LEVEL0);
writel_relaxed(0, sirfsoc_intc_base + SIRFSOC_INT_RISC_LEVEL1);
writel_relaxed(0, sirfsoc_intc_base + SIRFSOC_INT_RISC_MASK0);
writel_relaxed(0, sirfsoc_intc_base + SIRFSOC_INT_RISC_MASK1);
}
asmlinkage void __exception_irq_entry sirfsoc_handle_irq(struct pt_regs *regs)
{
u32 irqstat, irqnr;
irqstat = readl_relaxed(sirfsoc_intc_base + SIRFSOC_INIT_IRQ_ID);
irqnr = irqstat & 0xff;
handle_IRQ(irqnr, regs);
}
static struct of_device_id intc_ids[] = {
{ .compatible = "sirf,prima2-intc" },
{},
};
void __init sirfsoc_of_irq_init(void)
{
struct device_node *np;
np = of_find_matching_node(NULL, intc_ids);
if (!np)
return;
sirfsoc_intc_base = of_iomap(np, 0);
if (!sirfsoc_intc_base)
panic("unable to map intc cpu registers\n");
irq_domain_add_legacy(np, SIRFSOC_INTENAL_IRQ_END + 1, 0, 0,
&irq_domain_simple_ops, NULL);
of_node_put(np);
sirfsoc_irq_init();
}
struct sirfsoc_irq_status {
u32 mask0;
u32 mask1;
u32 level0;
u32 level1;
};
static struct sirfsoc_irq_status sirfsoc_irq_st;
static int sirfsoc_irq_suspend(void)
{
sirfsoc_irq_st.mask0 = readl_relaxed(sirfsoc_intc_base + SIRFSOC_INT_RISC_MASK0);
sirfsoc_irq_st.mask1 = readl_relaxed(sirfsoc_intc_base + SIRFSOC_INT_RISC_MASK1);
sirfsoc_irq_st.level0 = readl_relaxed(sirfsoc_intc_base + SIRFSOC_INT_RISC_LEVEL0);
sirfsoc_irq_st.level1 = readl_relaxed(sirfsoc_intc_base + SIRFSOC_INT_RISC_LEVEL1);
return 0;
}
static void sirfsoc_irq_resume(void)
{
writel_relaxed(sirfsoc_irq_st.mask0, sirfsoc_intc_base + SIRFSOC_INT_RISC_MASK0);
writel_relaxed(sirfsoc_irq_st.mask1, sirfsoc_intc_base + SIRFSOC_INT_RISC_MASK1);
writel_relaxed(sirfsoc_irq_st.level0, sirfsoc_intc_base + SIRFSOC_INT_RISC_LEVEL0);
writel_relaxed(sirfsoc_irq_st.level1, sirfsoc_intc_base + SIRFSOC_INT_RISC_LEVEL1);
}
static struct syscore_ops sirfsoc_irq_syscore_ops = {
.suspend = sirfsoc_irq_suspend,
.resume = sirfsoc_irq_resume,
};
static int __init sirfsoc_irq_pm_init(void)
{
register_syscore_ops(&sirfsoc_irq_syscore_ops);
return 0;
}
device_initcall(sirfsoc_irq_pm_init);

14
arch/arm/mach-prima2/lluart.c
View File

@ -9,8 +9,18 @@
#include <linux/kernel.h>
#include <asm/page.h>
#include <asm/mach/map.h>
#include <mach/map.h>
#include <mach/uart.h>
#include "common.h"
#if defined(CONFIG_DEBUG_SIRFPRIMA2_UART1)
#define SIRFSOC_UART1_PA_BASE 0xb0060000
#elif defined(CONFIG_DEBUG_SIRFMARCO_UART1)
#define SIRFSOC_UART1_PA_BASE 0xcc060000
#else
#define SIRFSOC_UART1_PA_BASE 0
#endif
#define SIRFSOC_UART1_VA_BASE SIRFSOC_VA(0x060000)
#define SIRFSOC_UART1_SIZE SZ_4K
void __init sirfsoc_map_lluart(void)
{

1
arch/arm/mach-prima2/platsmp.c
View File

@ -17,7 +17,6 @@
#include <asm/smp_scu.h>
#include <asm/cacheflush.h>
#include <asm/cputype.h>
#include <mach/map.h>
#include "common.h"

8
arch/arm/mach-realview/Kconfig
View File

@ -12,6 +12,8 @@ config REALVIEW_EB_A9MP
bool "Support Multicore Cortex-A9 Tile"
depends on MACH_REALVIEW_EB
select CPU_V7
select HAVE_ARM_SCU if SMP
select HAVE_ARM_TWD if LOCAL_TIMERS
select HAVE_SMP
select MIGHT_HAVE_CACHE_L2X0
help
@ -23,6 +25,8 @@ config REALVIEW_EB_ARM11MP
depends on MACH_REALVIEW_EB
select ARCH_HAS_BARRIERS if SMP
select CPU_V6K
select HAVE_ARM_SCU if SMP
select HAVE_ARM_TWD if LOCAL_TIMERS
select HAVE_SMP
select MIGHT_HAVE_CACHE_L2X0
help
@ -43,6 +47,8 @@ config MACH_REALVIEW_PB11MP
select ARCH_HAS_BARRIERS if SMP
select ARM_GIC
select CPU_V6K
select HAVE_ARM_SCU if SMP
select HAVE_ARM_TWD if LOCAL_TIMERS
select HAVE_PATA_PLATFORM
select HAVE_SMP
select MIGHT_HAVE_CACHE_L2X0
@ -85,6 +91,8 @@ config MACH_REALVIEW_PBX
bool "Support RealView(R) Platform Baseboard Explore"
select ARCH_SPARSEMEM_ENABLE if CPU_V7 && !REALVIEW_HIGH_PHYS_OFFSET
select ARM_GIC
select HAVE_ARM_SCU if SMP
select HAVE_ARM_TWD if LOCAL_TIMERS
select HAVE_PATA_PLATFORM
select HAVE_SMP
select MIGHT_HAVE_CACHE_L2X0

2
arch/arm/mach-s3c24xx/include/mach/debug-macro.S
View File

@ -98,4 +98,4 @@
/* include the reset of the code which will do the work */
#include <plat/debug-macro.S>
#include <debug/samsung.S>

2
arch/arm/mach-s3c64xx/include/mach/debug-macro.S
View File

@ -35,4 +35,4 @@
* will be fine with us.
*/
#include <plat/debug-macro.S>
#include <debug/samsung.S>

2
arch/arm/mach-s5p64x0/include/mach/debug-macro.S
View File

@ -30,4 +30,4 @@
#endif
.endm
#include <plat/debug-macro.S>
#include <debug/samsung.S>

2
arch/arm/mach-s5pc100/include/mach/debug-macro.S
View File

@ -36,4 +36,4 @@
* will be fine with us.
*/
#include <plat/debug-macro.S>
#include <debug/samsung.S>

1
arch/arm/mach-s5pc100/setup-sdhci-gpio.c
View File

@ -19,7 +19,6 @@
#include <linux/mmc/card.h>
#include <plat/gpio-cfg.h>
#include <plat/regs-sdhci.h>
#include <plat/sdhci.h>
void s5pc100_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width)

2
arch/arm/mach-s5pv210/include/mach/debug-macro.S
View File

@ -38,4 +38,4 @@
* will be fine with us.
*/
#include <plat/debug-macro.S>
#include <debug/samsung.S>

1
arch/arm/mach-s5pv210/setup-sdhci-gpio.c
View File

@ -20,7 +20,6 @@
#include <linux/mmc/card.h>
#include <plat/gpio-cfg.h>
#include <plat/regs-sdhci.h>
#include <plat/sdhci.h>
void s5pv210_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width)

105
arch/arm/mach-spear/Kconfig Normal file
View File

@ -0,0 +1,105 @@
#
# SPEAr Platform configuration file
#
menuconfig PLAT_SPEAR
bool "ST SPEAr Family" if ARCH_MULTI_V7 || ARCH_MULTI_V5
default PLAT_SPEAR_SINGLE
select ARCH_REQUIRE_GPIOLIB
select ARM_AMBA
select CLKDEV_LOOKUP
select CLKSRC_MMIO
select COMMON_CLK
select GENERIC_CLOCKEVENTS
select HAVE_CLK
if PLAT_SPEAR
config ARCH_SPEAR13XX
bool "ST SPEAr13xx"
depends on ARCH_MULTI_V7 || PLAT_SPEAR_SINGLE
select ARCH_HAS_CPUFREQ
select ARM_GIC
select CPU_V7
select GPIO_SPEAR_SPICS
select HAVE_ARM_SCU if SMP
select HAVE_ARM_TWD if LOCAL_TIMERS
select HAVE_SMP
select MIGHT_HAVE_CACHE_L2X0
select PINCTRL
select USE_OF
help
Supports for ARM's SPEAR13XX family
if ARCH_SPEAR13XX
config MACH_SPEAR1310
bool "SPEAr1310 Machine support with Device Tree"
select PINCTRL_SPEAR1310
help
Supports ST SPEAr1310 machine configured via the device-tree
config MACH_SPEAR1340
bool "SPEAr1340 Machine support with Device Tree"
select PINCTRL_SPEAR1340
help
Supports ST SPEAr1340 machine configured via the device-tree
endif #ARCH_SPEAR13XX
config ARCH_SPEAR3XX
bool "ST SPEAr3xx"
depends on ARCH_MULTI_V5 || PLAT_SPEAR_SINGLE
depends on !ARCH_SPEAR13XX
select ARM_VIC
select CPU_ARM926T
select PINCTRL
select USE_OF
help
Supports for ARM's SPEAR3XX family
if ARCH_SPEAR3XX
config MACH_SPEAR300
bool "SPEAr300 Machine support with Device Tree"
select PINCTRL_SPEAR300
help
Supports ST SPEAr300 machine configured via the device-tree
config MACH_SPEAR310
bool "SPEAr310 Machine support with Device Tree"
select PINCTRL_SPEAR310
help
Supports ST SPEAr310 machine configured via the device-tree
config MACH_SPEAR320
bool "SPEAr320 Machine support with Device Tree"
select PINCTRL_SPEAR320
help
Supports ST SPEAr320 machine configured via the device-tree
endif
config ARCH_SPEAR6XX
bool "ST SPEAr6XX"
depends on ARCH_MULTI_V5 || PLAT_SPEAR_SINGLE
depends on !ARCH_SPEAR13XX
select ARM_VIC
select CPU_ARM926T
help
Supports for ARM's SPEAR6XX family
config MACH_SPEAR600
def_bool y
depends on ARCH_SPEAR6XX
select USE_OF
help
Supports ST SPEAr600 boards configured via the device-treesource "arch/arm/mach-spear6xx/Kconfig"
config ARCH_SPEAR_AUTO
def_bool PLAT_SPEAR_SINGLE
depends on !ARCH_SPEAR13XX && !ARCH_SPEAR6XX
select ARCH_SPEAR3XX
endif

26
arch/arm/mach-spear/Makefile Normal file
View File

@ -0,0 +1,26 @@
#
# SPEAr Platform specific Makefile
#
ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include
# Common support
obj-y := restart.o time.o
obj-$(CONFIG_SMP) += headsmp.o platsmp.o
obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
obj-$(CONFIG_ARCH_SPEAR13XX) += spear13xx.o
obj-$(CONFIG_MACH_SPEAR1310) += spear1310.o
obj-$(CONFIG_MACH_SPEAR1340) += spear1340.o
obj-$(CONFIG_ARCH_SPEAR3XX) += spear3xx.o
obj-$(CONFIG_ARCH_SPEAR3XX) += pl080.o
obj-$(CONFIG_MACH_SPEAR300) += spear300.o
obj-$(CONFIG_MACH_SPEAR310) += spear310.o
obj-$(CONFIG_MACH_SPEAR320) += spear320.o
obj-$(CONFIG_ARCH_SPEAR6XX) += spear6xx.o
obj-$(CONFIG_ARCH_SPEAR6XX) += pl080.o
CFLAGS_hotplug.o += -march=armv7-a

0
arch/arm/mach-spear13xx/Makefile.boot → arch/arm/mach-spear/Makefile.boot
View File

30
arch/arm/mach-spear13xx/include/mach/generic.h → arch/arm/mach-spear/generic.h
View File

@ -1,9 +1,8 @@
/*
* arch/arm/mach-spear13xx/include/mach/generic.h
* spear machine family generic header file
*
* spear13xx machine family generic header file
*
* Copyright (C) 2012 ST Microelectronics
* Copyright (C) 2009-2012 ST Microelectronics
* Rajeev Kumar <rajeev-dlh.kumar@st.com>
* Viresh Kumar <viresh.linux@gmail.com>
*
* This file is licensed under the terms of the GNU General Public
@ -15,37 +14,46 @@
#define __MACH_GENERIC_H
#include <linux/dmaengine.h>
#include <linux/amba/pl08x.h>
#include <linux/init.h>
#include <asm/mach/time.h>
/* Add spear13xx structure declarations here */
extern void spear13xx_timer_init(void);
extern void spear3xx_timer_init(void);
extern struct pl022_ssp_controller pl022_plat_data;
extern struct pl08x_platform_data pl080_plat_data;
extern struct dw_dma_platform_data dmac_plat_data;
extern struct dw_dma_slave cf_dma_priv;
extern struct dw_dma_slave nand_read_dma_priv;
extern struct dw_dma_slave nand_write_dma_priv;
bool dw_dma_filter(struct dma_chan *chan, void *slave);
/* Add spear13xx family function declarations here */
void __init spear_setup_of_timer(void);
void __init spear3xx_clk_init(void __iomem *misc_base,
void __iomem *soc_config_base);
void __init spear3xx_map_io(void);
void __init spear3xx_dt_init_irq(void);
void __init spear6xx_clk_init(void __iomem *misc_base);
void __init spear13xx_map_io(void);
void __init spear13xx_l2x0_init(void);
bool dw_dma_filter(struct dma_chan *chan, void *slave);
void spear_restart(char, const char *);
void spear13xx_secondary_startup(void);
void __cpuinit spear13xx_cpu_die(unsigned int cpu);
extern struct smp_operations spear13xx_smp_ops;
#ifdef CONFIG_MACH_SPEAR1310
void __init spear1310_clk_init(void);
void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base);
#else
static inline void spear1310_clk_init(void) {}
static inline void spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base) {}
#endif
#ifdef CONFIG_MACH_SPEAR1340
void __init spear1340_clk_init(void);
void __init spear1340_clk_init(void __iomem *misc_base);
#else
static inline void spear1340_clk_init(void) {}
static inline void spear1340_clk_init(void __iomem *misc_base) {}
#endif
#endif /* __MACH_GENERIC_H */

0
arch/arm/mach-spear13xx/headsmp.S → arch/arm/mach-spear/headsmp.S
View File

0
arch/arm/mach-spear13xx/hotplug.c → arch/arm/mach-spear/hotplug.c
View File

0
arch/arm/plat-spear/include/plat/debug-macro.S → arch/arm/mach-spear/include/mach/debug-macro.S
View File

22
arch/arm/mach-spear6xx/include/mach/irqs.h → arch/arm/mach-spear/include/mach/irqs.h
View File

@ -1,10 +1,9 @@
/*
* arch/arm/mach-spear6xx/include/mach/irqs.h
* IRQ helper macros for spear machine family
*
* IRQ helper macros for SPEAr6xx machine family
*
* Copyright (C) 2009 ST Microelectronics
* Rajeev Kumar<rajeev-dlh.kumar@st.com>
* Copyright (C) 2009-2012 ST Microelectronics
* Rajeev Kumar <rajeev-dlh.kumar@st.com>
* Viresh Kumar <viresh.linux@gmail.com>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
@ -14,6 +13,11 @@
#ifndef __MACH_IRQS_H
#define __MACH_IRQS_H
#ifdef CONFIG_ARCH_SPEAR3XX
#define NR_IRQS 256
#endif
#ifdef CONFIG_ARCH_SPEAR6XX
/* IRQ definitions */
/* VIC 1 */
#define IRQ_VIC_END 64
@ -21,5 +25,11 @@
/* GPIO pins virtual irqs */
#define VIRTUAL_IRQS 24
#define NR_IRQS (IRQ_VIC_END + VIRTUAL_IRQS)
#endif
#endif /* __MACH_IRQS_H */
#ifdef CONFIG_ARCH_SPEAR13XX
#define IRQ_GIC_END 160
#define NR_IRQS IRQ_GIC_END
#endif
#endif /* __MACH_IRQS_H */

2
arch/arm/mach-spear3xx/include/mach/misc_regs.h → arch/arm/mach-spear/include/mach/misc_regs.h
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@ -16,7 +16,7 @@
#include <mach/spear.h>
#define MISC_BASE IOMEM(VA_SPEAR3XX_ICM3_MISC_REG_BASE)
#define MISC_BASE (VA_SPEAR_ICM3_MISC_REG_BASE)
#define DMA_CHN_CFG (MISC_BASE + 0x0A0)
#endif /* __MACH_MISC_REGS_H */

95
arch/arm/mach-spear/include/mach/spear.h Normal file
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@ -0,0 +1,95 @@
/*
* SPEAr3xx/6xx Machine family specific definition
*
* Copyright (C) 2009,2012 ST Microelectronics
* Rajeev Kumar<rajeev-dlh.kumar@st.com>
* Viresh Kumar <viresh.linux@gmail.com>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#ifndef __MACH_SPEAR_H
#define __MACH_SPEAR_H
#include <asm/memory.h>
#if defined(CONFIG_ARCH_SPEAR3XX) || defined (CONFIG_ARCH_SPEAR6XX)
/* ICM1 - Low speed connection */
#define SPEAR_ICM1_2_BASE UL(0xD0000000)
#define VA_SPEAR_ICM1_2_BASE IOMEM(0xFD000000)
#define SPEAR_ICM1_UART_BASE UL(0xD0000000)
#define VA_SPEAR_ICM1_UART_BASE (VA_SPEAR_ICM1_2_BASE - SPEAR_ICM1_2_BASE + SPEAR_ICM1_UART_BASE)
#define SPEAR3XX_ICM1_SSP_BASE UL(0xD0100000)
/* ML-1, 2 - Multi Layer CPU Subsystem */
#define SPEAR_ICM3_ML1_2_BASE UL(0xF0000000)
#define VA_SPEAR6XX_ML_CPU_BASE IOMEM(0xF0000000)
/* ICM3 - Basic Subsystem */
#define SPEAR_ICM3_SMI_CTRL_BASE UL(0xFC000000)
#define VA_SPEAR_ICM3_SMI_CTRL_BASE IOMEM(0xFC000000)
#define SPEAR_ICM3_DMA_BASE UL(0xFC400000)
#define SPEAR_ICM3_SYS_CTRL_BASE UL(0xFCA00000)
#define VA_SPEAR_ICM3_SYS_CTRL_BASE (VA_SPEAR_ICM3_SMI_CTRL_BASE - SPEAR_ICM3_SMI_CTRL_BASE + SPEAR_ICM3_SYS_CTRL_BASE)
#define SPEAR_ICM3_MISC_REG_BASE UL(0xFCA80000)
#define VA_SPEAR_ICM3_MISC_REG_BASE (VA_SPEAR_ICM3_SMI_CTRL_BASE - SPEAR_ICM3_SMI_CTRL_BASE + SPEAR_ICM3_MISC_REG_BASE)
/* Debug uart for linux, will be used for debug and uncompress messages */
#define SPEAR_DBG_UART_BASE SPEAR_ICM1_UART_BASE
#define VA_SPEAR_DBG_UART_BASE VA_SPEAR_ICM1_UART_BASE
/* Sysctl base for spear platform */
#define SPEAR_SYS_CTRL_BASE SPEAR_ICM3_SYS_CTRL_BASE
#define VA_SPEAR_SYS_CTRL_BASE VA_SPEAR_ICM3_SYS_CTRL_BASE
#endif /* SPEAR3xx || SPEAR6XX */
/* SPEAr320 Macros */
#define SPEAR320_SOC_CONFIG_BASE UL(0xB3000000)
#define VA_SPEAR320_SOC_CONFIG_BASE IOMEM(0xFE000000)
#ifdef CONFIG_ARCH_SPEAR13XX
#define PERIP_GRP2_BASE UL(0xB3000000)
#define VA_PERIP_GRP2_BASE IOMEM(0xFE000000)
#define MCIF_SDHCI_BASE UL(0xB3000000)
#define SYSRAM0_BASE UL(0xB3800000)
#define VA_SYSRAM0_BASE IOMEM(0xFE800000)
#define SYS_LOCATION (VA_SYSRAM0_BASE + 0x600)
#define PERIP_GRP1_BASE UL(0xE0000000)
#define VA_PERIP_GRP1_BASE IOMEM(0xFD000000)
#define UART_BASE UL(0xE0000000)
#define VA_UART_BASE IOMEM(0xFD000000)
#define SSP_BASE UL(0xE0100000)
#define MISC_BASE UL(0xE0700000)
#define VA_MISC_BASE IOMEM(0xFD700000)
#define A9SM_AND_MPMC_BASE UL(0xEC000000)
#define VA_A9SM_AND_MPMC_BASE IOMEM(0xFC000000)
#define SPEAR1310_RAS_BASE UL(0xD8400000)
#define VA_SPEAR1310_RAS_BASE IOMEM(UL(0xFA400000))
/* A9SM peripheral offsets */
#define A9SM_PERIP_BASE UL(0xEC800000)
#define VA_A9SM_PERIP_BASE IOMEM(0xFC800000)
#define VA_SCU_BASE (VA_A9SM_PERIP_BASE + 0x00)
#define L2CC_BASE UL(0xED000000)
#define VA_L2CC_BASE IOMEM(UL(0xFB000000))
/* others */
#define DMAC0_BASE UL(0xEA800000)
#define DMAC1_BASE UL(0xEB000000)
#define MCIF_CF_BASE UL(0xB2800000)
/* Debug uart for linux, will be used for debug and uncompress messages */
#define SPEAR_DBG_UART_BASE UART_BASE
#define VA_SPEAR_DBG_UART_BASE VA_UART_BASE
#endif /* SPEAR13XX */
#endif /* __MACH_SPEAR_H */

0
arch/arm/plat-spear/include/plat/timex.h → arch/arm/mach-spear/include/mach/timex.h
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0
arch/arm/plat-spear/include/plat/uncompress.h → arch/arm/mach-spear/include/mach/uncompress.h
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0
arch/arm/plat-spear/pl080.c → arch/arm/mach-spear/pl080.c
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