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ASoC: qdsp6: audioreach: add q6prm support
Add support to q6prm (Proxy Resource Manager) module used for clock resources Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Reviewed-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com> Link: https://lore.kernel.org/r/20211026111655.1702-17-srinivas.kandagatla@linaro.org Signed-off-by: Mark Brown <broonie@kernel.org>
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4 changed files with 285 additions and 0 deletions
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@ -97,6 +97,9 @@ config SND_SOC_QDSP6_APM
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select SND_SOC_QDSP6_APM_DAI
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select SND_SOC_QDSP6_APM_LPASS_DAI
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config SND_SOC_QDSP6_PRM
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tristate
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config SND_SOC_QDSP6
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tristate "SoC ALSA audio driver for QDSP6"
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depends on QCOM_APR
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@ -112,6 +115,7 @@ config SND_SOC_QDSP6
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select SND_SOC_QDSP6_ASM_DAI
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select SND_SOC_TOPOLOGY
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select SND_SOC_QDSP6_APM
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select SND_SOC_QDSP6_PRM
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help
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To add support for MSM QDSP6 Soc Audio.
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This will enable sound soc platform specific
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@ -15,3 +15,4 @@ obj-$(CONFIG_SND_SOC_QDSP6_ASM_DAI) += q6asm-dai.o
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obj-$(CONFIG_SND_SOC_QDSP6_APM) += snd-q6apm.o
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obj-$(CONFIG_SND_SOC_QDSP6_APM_DAI) += q6apm-dai.o
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obj-$(CONFIG_SND_SOC_QDSP6_APM_LPASS_DAI) += q6apm-lpass-dais.o
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obj-$(CONFIG_SND_SOC_QDSP6_PRM) += q6prm.o
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202
sound/soc/qcom/qdsp6/q6prm.c
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202
sound/soc/qcom/qdsp6/q6prm.c
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@ -0,0 +1,202 @@
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// SPDX-License-Identifier: GPL-2.0
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// Copyright (c) 2021, Linaro Limited
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#include <linux/slab.h>
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#include <linux/wait.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/delay.h>
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#include <linux/of_platform.h>
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#include <linux/jiffies.h>
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#include <linux/soc/qcom/apr.h>
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#include <dt-bindings/soc/qcom,gpr.h>
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#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
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#include "q6prm.h"
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#include "audioreach.h"
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struct q6prm {
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struct device *dev;
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gpr_device_t *gdev;
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wait_queue_head_t wait;
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struct gpr_ibasic_rsp_result_t result;
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struct mutex lock;
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};
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#define PRM_CMD_REQUEST_HW_RSC 0x0100100F
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#define PRM_CMD_RSP_REQUEST_HW_RSC 0x02001002
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#define PRM_CMD_RELEASE_HW_RSC 0x01001010
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#define PRM_CMD_RSP_RELEASE_HW_RSC 0x02001003
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#define PARAM_ID_RSC_HW_CORE 0x08001032
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#define PARAM_ID_RSC_LPASS_CORE 0x0800102B
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#define PARAM_ID_RSC_AUDIO_HW_CLK 0x0800102C
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struct prm_cmd_request_hw_core {
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struct apm_module_param_data param_data;
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uint32_t hw_clk_id;
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} __packed;
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struct prm_cmd_request_rsc {
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struct apm_module_param_data param_data;
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uint32_t num_clk_id;
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struct audio_hw_clk_cfg clock_id;
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} __packed;
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static int q6prm_send_cmd_sync(struct q6prm *prm, struct gpr_pkt *pkt, uint32_t rsp_opcode)
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{
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return audioreach_send_cmd_sync(prm->dev, prm->gdev, &prm->result, &prm->lock,
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NULL, &prm->wait, pkt, rsp_opcode);
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}
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static int q6prm_set_hw_core_req(struct device *dev, uint32_t hw_block_id, bool enable)
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{
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struct q6prm *prm = dev_get_drvdata(dev->parent);
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struct apm_module_param_data *param_data;
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struct prm_cmd_request_hw_core *req;
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gpr_device_t *gdev = prm->gdev;
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uint32_t opcode, rsp_opcode;
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struct gpr_pkt *pkt;
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int rc;
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if (enable) {
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opcode = PRM_CMD_REQUEST_HW_RSC;
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rsp_opcode = PRM_CMD_RSP_REQUEST_HW_RSC;
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} else {
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opcode = PRM_CMD_RELEASE_HW_RSC;
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rsp_opcode = PRM_CMD_RSP_RELEASE_HW_RSC;
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}
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pkt = audioreach_alloc_cmd_pkt(sizeof(*req), opcode, 0, gdev->svc.id, GPR_PRM_MODULE_IID);
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if (IS_ERR(pkt))
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return PTR_ERR(pkt);
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req = (void *)pkt + GPR_HDR_SIZE + APM_CMD_HDR_SIZE;
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param_data = &req->param_data;
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param_data->module_instance_id = GPR_PRM_MODULE_IID;
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param_data->error_code = 0;
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param_data->param_id = PARAM_ID_RSC_HW_CORE;
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param_data->param_size = sizeof(*req) - APM_MODULE_PARAM_DATA_SIZE;
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req->hw_clk_id = hw_block_id;
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rc = q6prm_send_cmd_sync(prm, pkt, rsp_opcode);
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kfree(pkt);
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return rc;
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}
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int q6prm_vote_lpass_core_hw(struct device *dev, uint32_t hw_block_id,
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const char *client_name, uint32_t *client_handle)
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{
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return q6prm_set_hw_core_req(dev, hw_block_id, true);
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}
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EXPORT_SYMBOL_GPL(q6prm_vote_lpass_core_hw);
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int q6prm_unvote_lpass_core_hw(struct device *dev, uint32_t hw_block_id, uint32_t client_handle)
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{
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return q6prm_set_hw_core_req(dev, hw_block_id, false);
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}
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EXPORT_SYMBOL_GPL(q6prm_unvote_lpass_core_hw);
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int q6prm_set_lpass_clock(struct device *dev, int clk_id, int clk_attr, int clk_root,
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unsigned int freq)
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{
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struct q6prm *prm = dev_get_drvdata(dev->parent);
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struct apm_module_param_data *param_data;
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struct prm_cmd_request_rsc *req;
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gpr_device_t *gdev = prm->gdev;
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struct gpr_pkt *pkt;
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int rc;
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pkt = audioreach_alloc_cmd_pkt(sizeof(*req), PRM_CMD_REQUEST_HW_RSC, 0, gdev->svc.id,
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GPR_PRM_MODULE_IID);
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if (IS_ERR(pkt))
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return PTR_ERR(pkt);
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req = (void *)pkt + GPR_HDR_SIZE + APM_CMD_HDR_SIZE;
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param_data = &req->param_data;
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param_data->module_instance_id = GPR_PRM_MODULE_IID;
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param_data->error_code = 0;
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param_data->param_id = PARAM_ID_RSC_AUDIO_HW_CLK;
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param_data->param_size = sizeof(*req) - APM_MODULE_PARAM_DATA_SIZE;
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req->num_clk_id = 1;
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req->clock_id.clock_id = clk_id;
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req->clock_id.clock_freq = freq;
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req->clock_id.clock_attri = clk_attr;
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req->clock_id.clock_root = clk_root;
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rc = q6prm_send_cmd_sync(prm, pkt, PRM_CMD_RSP_REQUEST_HW_RSC);
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kfree(pkt);
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return rc;
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}
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EXPORT_SYMBOL_GPL(q6prm_set_lpass_clock);
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static int prm_callback(struct gpr_resp_pkt *data, void *priv, int op)
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{
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gpr_device_t *gdev = priv;
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struct q6prm *prm = dev_get_drvdata(&gdev->dev);
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struct gpr_ibasic_rsp_result_t *result;
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struct gpr_hdr *hdr = &data->hdr;
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switch (hdr->opcode) {
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case PRM_CMD_RSP_REQUEST_HW_RSC:
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case PRM_CMD_RSP_RELEASE_HW_RSC:
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result = data->payload;
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prm->result.opcode = hdr->opcode;
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prm->result.status = result->status;
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wake_up(&prm->wait);
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break;
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default:
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break;
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}
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return 0;
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}
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static int prm_probe(gpr_device_t *gdev)
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{
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struct device *dev = &gdev->dev;
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struct q6prm *cc;
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cc = devm_kzalloc(dev, sizeof(*cc), GFP_KERNEL);
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if (!cc)
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return -ENOMEM;
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cc->dev = dev;
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cc->gdev = gdev;
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mutex_init(&cc->lock);
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init_waitqueue_head(&cc->wait);
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dev_set_drvdata(dev, cc);
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return devm_of_platform_populate(dev);
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}
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#ifdef CONFIG_OF
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static const struct of_device_id prm_device_id[] = {
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{ .compatible = "qcom,q6prm" },
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{},
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};
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MODULE_DEVICE_TABLE(of, prm_device_id);
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#endif
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static gpr_driver_t prm_driver = {
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.probe = prm_probe,
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.gpr_callback = prm_callback,
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.driver = {
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.name = "qcom-prm",
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.of_match_table = of_match_ptr(prm_device_id),
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},
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};
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module_gpr_driver(prm_driver);
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MODULE_DESCRIPTION("Audio Process Manager");
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MODULE_LICENSE("GPL");
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78
sound/soc/qcom/qdsp6/q6prm.h
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78
sound/soc/qcom/qdsp6/q6prm.h
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/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __Q6PRM_H__
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#define __Q6PRM_H__
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/* Clock ID for Primary I2S IBIT */
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#define Q6PRM_LPASS_CLK_ID_PRI_MI2S_IBIT 0x100
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/* Clock ID for Primary I2S EBIT */
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#define Q6PRM_LPASS_CLK_ID_PRI_MI2S_EBIT 0x101
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/* Clock ID for Secondary I2S IBIT */
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#define Q6PRM_LPASS_CLK_ID_SEC_MI2S_IBIT 0x102
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/* Clock ID for Secondary I2S EBIT */
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#define Q6PRM_LPASS_CLK_ID_SEC_MI2S_EBIT 0x103
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/* Clock ID for Tertiary I2S IBIT */
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#define Q6PRM_LPASS_CLK_ID_TER_MI2S_IBIT 0x104
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/* Clock ID for Tertiary I2S EBIT */
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#define Q6PRM_LPASS_CLK_ID_TER_MI2S_EBIT 0x105
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/* Clock ID for Quartnery I2S IBIT */
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#define Q6PRM_LPASS_CLK_ID_QUAD_MI2S_IBIT 0x106
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/* Clock ID for Quartnery I2S EBIT */
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#define Q6PRM_LPASS_CLK_ID_QUAD_MI2S_EBIT 0x107
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/* Clock ID for Speaker I2S IBIT */
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#define Q6PRM_LPASS_CLK_ID_SPEAKER_I2S_IBIT 0x108
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/* Clock ID for Speaker I2S EBIT */
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#define Q6PRM_LPASS_CLK_ID_SPEAKER_I2S_EBIT 0x109
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/* Clock ID for Speaker I2S OSR */
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#define Q6PRM_LPASS_CLK_ID_SPEAKER_I2S_OSR 0x10A
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/* Clock ID for QUINARY I2S IBIT */
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#define Q6PRM_LPASS_CLK_ID_QUI_MI2S_IBIT 0x10B
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/* Clock ID for QUINARY I2S EBIT */
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#define Q6PRM_LPASS_CLK_ID_QUI_MI2S_EBIT 0x10C
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/* Clock ID for SENARY I2S IBIT */
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#define Q6PRM_LPASS_CLK_ID_SEN_MI2S_IBIT 0x10D
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/* Clock ID for SENARY I2S EBIT */
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#define Q6PRM_LPASS_CLK_ID_SEN_MI2S_EBIT 0x10E
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/* Clock ID for INT0 I2S IBIT */
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#define Q6PRM_LPASS_CLK_ID_INT0_MI2S_IBIT 0x10F
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/* Clock ID for INT1 I2S IBIT */
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#define Q6PRM_LPASS_CLK_ID_INT1_MI2S_IBIT 0x110
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/* Clock ID for INT2 I2S IBIT */
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#define Q6PRM_LPASS_CLK_ID_INT2_MI2S_IBIT 0x111
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/* Clock ID for INT3 I2S IBIT */
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#define Q6PRM_LPASS_CLK_ID_INT3_MI2S_IBIT 0x112
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/* Clock ID for INT4 I2S IBIT */
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#define Q6PRM_LPASS_CLK_ID_INT4_MI2S_IBIT 0x113
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/* Clock ID for INT5 I2S IBIT */
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#define Q6PRM_LPASS_CLK_ID_INT5_MI2S_IBIT 0x114
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/* Clock ID for INT6 I2S IBIT */
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#define Q6PRM_LPASS_CLK_ID_INT6_MI2S_IBIT 0x115
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/* Clock ID for QUINARY MI2S OSR CLK */
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#define Q6PRM_LPASS_CLK_ID_QUI_MI2S_OSR 0x116
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#define Q6PRM_LPASS_CLK_ID_WSA_CORE_MCLK 0x305
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#define Q6PRM_LPASS_CLK_ID_WSA_CORE_NPL_MCLK 0x306
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#define Q6PRM_LPASS_CLK_ID_VA_CORE_MCLK 0x307
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#define Q6PRM_LPASS_CLK_ID_VA_CORE_2X_MCLK 0x308
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#define Q6PRM_LPASS_CLK_ID_TX_CORE_MCLK 0x30c
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#define Q6PRM_LPASS_CLK_ID_TX_CORE_NPL_MCLK 0x30d
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#define Q6PRM_LPASS_CLK_ID_RX_CORE_MCLK 0x30e
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#define Q6PRM_LPASS_CLK_ID_RX_CORE_NPL_MCLK 0x30f
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#define Q6PRM_LPASS_CLK_SRC_INTERNAL 1
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#define Q6PRM_LPASS_CLK_ROOT_DEFAULT 0
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#define Q6PRM_HW_CORE_ID_LPASS 1
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#define Q6PRM_HW_CORE_ID_DCODEC 2
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int q6prm_set_lpass_clock(struct device *dev, int clk_id, int clk_attr,
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int clk_root, unsigned int freq);
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int q6prm_vote_lpass_core_hw(struct device *dev, uint32_t hw_block_id,
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const char *client_name, uint32_t *client_handle);
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int q6prm_unvote_lpass_core_hw(struct device *dev, uint32_t hw_block_id,
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uint32_t client_handle);
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#endif /* __Q6PRM_H__ */
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