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davinci: move PLL wait time values to clock.h

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As suspend support is added, the code supporting
the suspend operation needs to bypass PLLs and
needs to access the same wait time values as the
PLL code in clock.c.

To facilitate this, move the PLL wait times to
clock.h where they can be accessed by suspend code.

Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
This commit is contained in:
Sekhar Nori 2009-11-16 17:21:33 +05:30 committed by Kevin Hilman
parent d2de05827c
commit 9a219a9ecf
2 changed files with 18 additions and 12 deletions
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15
arch/arm/mach-davinci/clock.c
View file

@ -376,7 +376,7 @@ int davinci_set_pllrate(struct pll_data *pll, unsigned int prediv,
locktime = ((2000 * prediv) / 100); locktime = ((2000 * prediv) / 100);
prediv = (prediv - 1) | PLLDIV_EN; prediv = (prediv - 1) | PLLDIV_EN;
} else { } else {
locktime = 20; locktime = PLL_LOCK_TIME;
} }
if (postdiv) if (postdiv)
postdiv = (postdiv - 1) | PLLDIV_EN; postdiv = (postdiv - 1) | PLLDIV_EN;
@ -389,12 +389,7 @@ int davinci_set_pllrate(struct pll_data *pll, unsigned int prediv,
ctrl &= ~(PLLCTL_PLLENSRC | PLLCTL_PLLEN); ctrl &= ~(PLLCTL_PLLENSRC | PLLCTL_PLLEN);
__raw_writel(ctrl, pll->base + PLLCTL); __raw_writel(ctrl, pll->base + PLLCTL);
/* udelay(PLL_BYPASS_TIME);
* Wait for 4 OSCIN/CLKIN cycles to ensure that the PLLC has switched
* to bypass mode. Delay of 1us ensures we are good for all > 4MHz
* OSCIN/CLKIN inputs. Typically the input is ~25MHz.
*/
udelay(1);
/* Reset and enable PLL */ /* Reset and enable PLL */
ctrl &= ~(PLLCTL_PLLRST | PLLCTL_PLLDIS); ctrl &= ~(PLLCTL_PLLRST | PLLCTL_PLLDIS);
@ -408,11 +403,7 @@ int davinci_set_pllrate(struct pll_data *pll, unsigned int prediv,
if (pll->flags & PLL_HAS_POSTDIV) if (pll->flags & PLL_HAS_POSTDIV)
__raw_writel(postdiv, pll->base + POSTDIV); __raw_writel(postdiv, pll->base + POSTDIV);
/* udelay(PLL_RESET_TIME);
* Wait for PLL to reset properly, OMAP-L138 datasheet says
* 'min' time = 125ns
*/
udelay(1);
/* Bring PLL out of reset */ /* Bring PLL out of reset */
ctrl |= PLLCTL_PLLRST; ctrl |= PLLCTL_PLLRST;

15
arch/arm/mach-davinci/clock.h
View file

@ -53,6 +53,21 @@
#define PLLDIV_EN BIT(15) #define PLLDIV_EN BIT(15)
#define PLLDIV_RATIO_MASK 0x1f #define PLLDIV_RATIO_MASK 0x1f
/*
* OMAP-L138 system reference guide recommends a wait for 4 OSCIN/CLKIN
* cycles to ensure that the PLLC has switched to bypass mode. Delay of 1us
* ensures we are good for all > 4MHz OSCIN/CLKIN inputs. Typically the input
* is ~25MHz. Units are micro seconds.
*/
#define PLL_BYPASS_TIME 1
/* From OMAP-L138 datasheet table 6-4. Units are micro seconds */
#define PLL_RESET_TIME 1
/*
* From OMAP-L138 datasheet table 6-4; assuming prediv = 1, sqrt(pllm) = 4
* Units are micro seconds.
*/
#define PLL_LOCK_TIME 20
struct pll_data { struct pll_data {
u32 phys_base; u32 phys_base;
void __iomem *base; void __iomem *base;