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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
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rk3308 io-domains, and some default settings for bits in the general
register files for rk3128 and the new rk3576 soc. -----BEGIN PGP SIGNATURE----- iQFEBAABCAAuFiEE7v+35S2Q1vLNA3Lx86Z5yZzRHYEFAmbU3/wQHGhlaWtvQHNu dGVjaC5kZQAKCRDzpnnJnNEdgTtZCACdufbwkqdabyJXm0FK81HUpHCWADzsgNwk j5F7X7V4xXLqSjD7jWEeqhT6ZH8un2Nd2cOFh0E2RrPfuBi6Jl/DVyFWQE5s19j+ duso5cw7E1MiJUDB9TjXD7RAJj2HQYzHFgqeEaigE7j0V7LFug72O4fOg27GUmH4 soFA5VOVuWB4GzPgqCBFd6Pv7Zi+oikg8gTugyKeNrFUWqunFgVTBNN1t0eoE26Q Ycxfth8ovd6CI3o6SxeZu1Yge/Aum6jjhRn6CBcQIBDOyMCJaV1eM5c9LzkB+4sc aMVVe2ko/nZ74xiCEUuhrH2VJQ5f/HeSaVvrdOHApoyKUQ69eKq+ =QvOa -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEiK/NIGsWEZVxh/FrYKtH/8kJUicFAmbVicMACgkQYKtH/8kJ UicAlA/+Iv8qCNc33YNV6bQctYW9E6cJU6EViasPu8fK8E7ZKMqOPkULP5uY09Ck LHlq6hpYzwwhCZbgBjiN8+yAXHsp99qRLrWOXHveYAwFH5Wy1xox98819gnvpFwu w5YkebSnrcHFVDFnYtXBtxKHdRLxaAFoFLXGE8YW9WkqVe2ZamErup7mo/3QVXVF cTh5rYkuyMc0M9ZbIfBsO8aBKZmi/yxornW9u5et/5cuCp820ZdskzKHIXUFd8ub I9gf/kiLQYhrqPj/IlVxHB+MhrPHWdDfM64CsO2mFi+TdDHbJm0uv/WBR8ftQzga FzODKHN+bIOU4WFjm0O5fS4RYiHnh1Aek0yCDzzatr+CMELho2uAQKhrgRzGGC9M KDtNtzacpfweO/XypMbhZ08ty7MUFDH/EyWWUnZtNS8/C3VSHe5PS7kyjotwZVp6 R/jbGWN1jY0D2zcUaH3D3Q8kMaihdP5EYDZtd+vVxb3HNNb85DMqd3ljRIDjQMW/ RUW+Dwu9G+uU4DfBAvcuz9RtyoACEYuKrxWnUo3PePCrWual9XBXtbOJfeNRXEec cEC6O9EuE44KFUwpK0d+Ak2SmtbJ2TP0v1yacgLRB11R8ymhsApb0VfdqqE7NAuH ZbwWgqehwWiPnBrbtr4uVmAeY2ad0a2wDRLpdWD3uwVXl07qc9M= =XanP -----END PGP SIGNATURE----- Merge tag 'v6.12-rockchip-drivers-1' of https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into soc/drivers rk3308 io-domains, and some default settings for bits in the general register files for rk3128 and the new rk3576 soc. * tag 'v6.12-rockchip-drivers-1' of https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: soc: rockchip: grf: Add rk3576 default GRF values dt-bindings: soc: rockchip: Add rk3576 syscon compatibles soc: rockchip: grf: Set RK3128's vpu main clock soc: rockchip: io-domain: Add RK3308 IO voltage domains dt-bindings: power: rockchip: Document RK3308 IO voltage domains Link: https://lore.kernel.org/r/23316481.ssLaC8jLEa@diego Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
9a2f5cbf8f
4 changed files with 111 additions and 1 deletions
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@ -50,6 +50,7 @@ properties:
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- rockchip,rk3188-io-voltage-domain
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- rockchip,rk3228-io-voltage-domain
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- rockchip,rk3288-io-voltage-domain
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- rockchip,rk3308-io-voltage-domain
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- rockchip,rk3328-io-voltage-domain
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- rockchip,rk3368-io-voltage-domain
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- rockchip,rk3368-pmu-io-voltage-domain
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@ -71,6 +72,7 @@ allOf:
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- $ref: "#/$defs/rk3188"
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- $ref: "#/$defs/rk3228"
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- $ref: "#/$defs/rk3288"
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- $ref: "#/$defs/rk3308"
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- $ref: "#/$defs/rk3328"
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- $ref: "#/$defs/rk3368"
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- $ref: "#/$defs/rk3368-pmu"
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@ -194,6 +196,28 @@ $defs:
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wifi-supply:
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description: The supply connected to APIO3_VDD. Also known as SDIO0.
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rk3308:
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if:
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properties:
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compatible:
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contains:
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const: rockchip,rk3308-io-voltage-domain
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then:
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properties:
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vccio0-supply:
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description: The supply connected to VCCIO0.
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vccio1-supply:
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description: The supply connected to VCCIO1.
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vccio2-supply:
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description: The supply connected to VCCIO2.
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vccio3-supply:
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description: The supply connected to VCCIO3.
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vccio4-supply:
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description: The supply connected to VCCIO4.
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vccio5-supply:
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description: The supply connected to VCCIO5.
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rk3328:
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if:
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properties:
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@ -20,6 +20,20 @@ properties:
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- rockchip,rk3568-pipe-grf
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- rockchip,rk3568-pipe-phy-grf
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- rockchip,rk3568-usb2phy-grf
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- rockchip,rk3576-bigcore-grf
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- rockchip,rk3576-cci-grf
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- rockchip,rk3576-gpu-grf
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- rockchip,rk3576-litcore-grf
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- rockchip,rk3576-npu-grf
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- rockchip,rk3576-php-grf
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- rockchip,rk3576-pipe-phy-grf
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- rockchip,rk3576-pmu1-grf
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- rockchip,rk3576-sdgmac-grf
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- rockchip,rk3576-sys-grf
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- rockchip,rk3576-usb-grf
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- rockchip,rk3576-usbdpphy-grf
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- rockchip,rk3576-vo0-grf
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- rockchip,rk3576-vop-grf
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- rockchip,rk3588-bigcore0-grf
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- rockchip,rk3588-bigcore1-grf
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- rockchip,rk3588-hdptxphy-grf
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@ -58,6 +72,8 @@ properties:
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- rockchip,rk3399-pmugrf
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- rockchip,rk3568-grf
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- rockchip,rk3568-pmugrf
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- rockchip,rk3576-ioc-grf
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- rockchip,rk3576-pmu0-grf
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- rockchip,rk3588-usb2phy-grf
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- rockchip,rv1108-grf
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- rockchip,rv1108-pmugrf
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@ -41,9 +41,11 @@ static const struct rockchip_grf_info rk3036_grf __initconst = {
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};
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#define RK3128_GRF_SOC_CON0 0x140
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#define RK3128_GRF_SOC_CON1 0x144
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static const struct rockchip_grf_value rk3128_defaults[] __initconst = {
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{ "jtag switching", RK3128_GRF_SOC_CON0, HIWORD_UPDATE(0, 1, 8) },
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{ "vpu main clock", RK3128_GRF_SOC_CON1, HIWORD_UPDATE(0, 1, 10) },
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};
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static const struct rockchip_grf_info rk3128_grf __initconst = {
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@ -121,6 +123,29 @@ static const struct rockchip_grf_info rk3566_pipegrf __initconst = {
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.num_values = ARRAY_SIZE(rk3566_defaults),
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};
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#define RK3576_SYSGRF_SOC_CON1 0x0004
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static const struct rockchip_grf_value rk3576_defaults_sys_grf[] __initconst = {
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{ "i3c0 weakpull", RK3576_SYSGRF_SOC_CON1, HIWORD_UPDATE(3, 3, 6) },
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{ "i3c1 weakpull", RK3576_SYSGRF_SOC_CON1, HIWORD_UPDATE(3, 3, 8) },
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};
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static const struct rockchip_grf_info rk3576_sysgrf __initconst = {
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.values = rk3576_defaults_sys_grf,
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.num_values = ARRAY_SIZE(rk3576_defaults_sys_grf),
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};
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#define RK3576_IOCGRF_MISC_CON 0x04F0
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static const struct rockchip_grf_value rk3576_defaults_ioc_grf[] __initconst = {
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{ "jtag switching", RK3576_IOCGRF_MISC_CON, HIWORD_UPDATE(0, 1, 1) },
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};
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static const struct rockchip_grf_info rk3576_iocgrf __initconst = {
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.values = rk3576_defaults_ioc_grf,
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.num_values = ARRAY_SIZE(rk3576_defaults_ioc_grf),
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};
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#define RK3588_GRF_SOC_CON6 0x0318
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static const struct rockchip_grf_value rk3588_defaults[] __initconst = {
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@ -132,7 +157,6 @@ static const struct rockchip_grf_info rk3588_sysgrf __initconst = {
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.num_values = ARRAY_SIZE(rk3588_defaults),
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};
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static const struct of_device_id rockchip_grf_dt_match[] __initconst = {
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{
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.compatible = "rockchip,rk3036-grf",
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@ -158,6 +182,12 @@ static const struct of_device_id rockchip_grf_dt_match[] __initconst = {
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}, {
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.compatible = "rockchip,rk3566-pipe-grf",
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.data = (void *)&rk3566_pipegrf,
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}, {
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.compatible = "rockchip,rk3576-sys-grf",
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.data = (void *)&rk3576_sysgrf,
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}, {
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.compatible = "rockchip,rk3576-ioc-grf",
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.data = (void *)&rk3576_iocgrf,
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}, {
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.compatible = "rockchip,rk3588-sys-grf",
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.data = (void *)&rk3588_sysgrf,
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@ -39,6 +39,10 @@
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#define RK3288_SOC_CON2_FLASH0 BIT(7)
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#define RK3288_SOC_FLASH_SUPPLY_NUM 2
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#define RK3308_SOC_CON0 0x300
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#define RK3308_SOC_CON0_VCCIO3 BIT(8)
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#define RK3308_SOC_VCCIO3_SUPPLY_NUM 3
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#define RK3328_SOC_CON4 0x410
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#define RK3328_SOC_CON4_VCCIO2 BIT(7)
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#define RK3328_SOC_VCCIO2_SUPPLY_NUM 1
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@ -229,6 +233,25 @@ static void rk3288_iodomain_init(struct rockchip_iodomain *iod)
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dev_warn(iod->dev, "couldn't update flash0 ctrl\n");
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}
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static void rk3308_iodomain_init(struct rockchip_iodomain *iod)
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{
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int ret;
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u32 val;
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/* if no vccio3 supply we should leave things alone */
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if (!iod->supplies[RK3308_SOC_VCCIO3_SUPPLY_NUM].reg)
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return;
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/*
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* set vccio3 iodomain to also use this framework
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* instead of a special gpio.
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*/
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val = RK3308_SOC_CON0_VCCIO3 | (RK3308_SOC_CON0_VCCIO3 << 16);
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ret = regmap_write(iod->grf, RK3308_SOC_CON0, val);
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if (ret < 0)
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dev_warn(iod->dev, "couldn't update vccio3 vsel ctrl\n");
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}
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static void rk3328_iodomain_init(struct rockchip_iodomain *iod)
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{
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int ret;
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@ -376,6 +399,19 @@ static const struct rockchip_iodomain_soc_data soc_data_rk3288 = {
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.init = rk3288_iodomain_init,
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};
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static const struct rockchip_iodomain_soc_data soc_data_rk3308 = {
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.grf_offset = 0x300,
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.supply_names = {
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"vccio0",
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"vccio1",
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"vccio2",
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"vccio3",
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"vccio4",
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"vccio5",
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},
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.init = rk3308_iodomain_init,
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};
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static const struct rockchip_iodomain_soc_data soc_data_rk3328 = {
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.grf_offset = 0x410,
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.supply_names = {
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@ -528,6 +564,10 @@ static const struct of_device_id rockchip_iodomain_match[] = {
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.compatible = "rockchip,rk3288-io-voltage-domain",
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.data = &soc_data_rk3288
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},
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{
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.compatible = "rockchip,rk3308-io-voltage-domain",
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.data = &soc_data_rk3308
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},
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{
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.compatible = "rockchip,rk3328-io-voltage-domain",
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.data = &soc_data_rk3328
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