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synced 2024-08-26 19:00:25 +00:00
drm/nv50: switch to indirect push buffer controls
PFIFO on G80 and up has a new mode where the main ring buffer is simply a ring of pointers to indirect buffers containing the actual command/data packets. In order to be able to implement index buffers in the 3D driver we need to be able to submit data-only push buffers right after the cmd packet header, which is only possible using the new command submission method. This commit doesn't make it possible to implement index buffers yet, some userspace interface changes will be required, but it does allow for testing/debugging of the hardware-side support in the meantime. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
parent
ff9e5279b1
commit
9a391ad8a2
6 changed files with 155 additions and 15 deletions
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@ -47,12 +47,23 @@ nouveau_debugfs_channel_info(struct seq_file *m, void *data)
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seq_printf(m, " cur: 0x%08x\n", chan->dma.cur << 2);
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seq_printf(m, " put: 0x%08x\n", chan->dma.put << 2);
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seq_printf(m, " free: 0x%08x\n", chan->dma.free << 2);
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if (chan->dma.ib_max) {
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seq_printf(m, " ib max: 0x%08x\n", chan->dma.ib_max);
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seq_printf(m, " ib put: 0x%08x\n", chan->dma.ib_put);
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seq_printf(m, " ib free: 0x%08x\n", chan->dma.ib_free);
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}
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seq_printf(m, "gpu fifo state:\n");
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seq_printf(m, " get: 0x%08x\n",
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nvchan_rd32(chan, chan->user_get));
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seq_printf(m, " put: 0x%08x\n",
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nvchan_rd32(chan, chan->user_put));
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if (chan->dma.ib_max) {
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seq_printf(m, " ib get: 0x%08x\n",
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nvchan_rd32(chan, 0x88));
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seq_printf(m, " ib put: 0x%08x\n",
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nvchan_rd32(chan, 0x8c));
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}
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seq_printf(m, "last fence : %d\n", chan->fence.sequence);
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seq_printf(m, "last signalled: %d\n", chan->fence.sequence_ack);
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@ -32,7 +32,22 @@
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void
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nouveau_dma_pre_init(struct nouveau_channel *chan)
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{
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chan->dma.max = (chan->pushbuf_bo->bo.mem.size >> 2) - 2;
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struct drm_nouveau_private *dev_priv = chan->dev->dev_private;
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struct nouveau_bo *pushbuf = chan->pushbuf_bo;
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if (dev_priv->card_type == NV_50) {
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const int ib_size = pushbuf->bo.mem.size / 2;
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chan->dma.ib_base = (pushbuf->bo.mem.size - ib_size) >> 2;
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chan->dma.ib_max = (ib_size / 8) - 1;
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chan->dma.ib_put = 0;
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chan->dma.ib_free = chan->dma.ib_max - chan->dma.ib_put;
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chan->dma.max = (pushbuf->bo.mem.size - ib_size) >> 2;
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} else {
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chan->dma.max = (pushbuf->bo.mem.size >> 2) - 2;
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}
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chan->dma.put = 0;
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chan->dma.cur = chan->dma.put;
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chan->dma.free = chan->dma.max - chan->dma.cur;
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@ -162,12 +177,101 @@ READ_GET(struct nouveau_channel *chan, uint32_t *prev_get, uint32_t *timeout)
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return (val - chan->pushbuf_base) >> 2;
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}
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void
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nv50_dma_push(struct nouveau_channel *chan, struct nouveau_bo *bo,
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int delta, int dwords)
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{
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struct nouveau_bo *pb = chan->pushbuf_bo;
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uint64_t offset = (bo->bo.mem.mm_node->start << PAGE_SHIFT) + delta;
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int ip = (chan->dma.ib_put * 2) + chan->dma.ib_base;
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BUG_ON(chan->dma.ib_free < 1);
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nouveau_bo_wr32(pb, ip++, offset);
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nouveau_bo_wr32(pb, ip++, dwords << 10);
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chan->dma.ib_put = (chan->dma.ib_put + 1) & chan->dma.ib_max;
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nvchan_wr32(chan, 0x8c, chan->dma.ib_put);
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chan->dma.ib_free--;
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}
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static int
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nv50_dma_push_wait(struct nouveau_channel *chan, int count)
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{
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uint32_t cnt = 0, prev_get = 0;
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while (chan->dma.ib_free < count) {
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uint32_t get = nvchan_rd32(chan, 0x88);
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if (get != prev_get) {
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prev_get = get;
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cnt = 0;
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}
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if ((++cnt & 0xff) == 0) {
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DRM_UDELAY(1);
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if (cnt > 100000)
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return -EBUSY;
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}
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chan->dma.ib_free = get - chan->dma.ib_put;
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if (chan->dma.ib_free <= 0)
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chan->dma.ib_free += chan->dma.ib_max + 1;
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}
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return 0;
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}
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static int
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nv50_dma_wait(struct nouveau_channel *chan, int slots, int count)
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{
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uint32_t cnt = 0, prev_get = 0;
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int ret;
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ret = nv50_dma_push_wait(chan, slots + 1);
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if (unlikely(ret))
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return ret;
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while (chan->dma.free < count) {
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int get = READ_GET(chan, &prev_get, &cnt);
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if (unlikely(get < 0)) {
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if (get == -EINVAL)
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continue;
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return get;
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}
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if (get <= chan->dma.cur) {
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chan->dma.free = chan->dma.max - chan->dma.cur;
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if (chan->dma.free >= count)
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break;
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FIRE_RING(chan);
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do {
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get = READ_GET(chan, &prev_get, &cnt);
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if (unlikely(get < 0)) {
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if (get == -EINVAL)
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continue;
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return get;
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}
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} while (get == 0);
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chan->dma.cur = 0;
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chan->dma.put = 0;
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}
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chan->dma.free = get - chan->dma.cur - 1;
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}
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return 0;
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}
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int
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nouveau_dma_wait(struct nouveau_channel *chan, int size)
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nouveau_dma_wait(struct nouveau_channel *chan, int slots, int size)
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{
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uint32_t prev_get = 0, cnt = 0;
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int get;
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if (chan->dma.ib_max)
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return nv50_dma_wait(chan, slots, size);
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while (chan->dma.free < size) {
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get = READ_GET(chan, &prev_get, &cnt);
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if (unlikely(get == -EBUSY))
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@ -31,6 +31,9 @@
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#define NOUVEAU_DMA_DEBUG 0
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#endif
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void nv50_dma_push(struct nouveau_channel *, struct nouveau_bo *,
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int delta, int dwords);
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/*
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* There's a hw race condition where you can't jump to your PUT offset,
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* to avoid this we jump to offset + SKIPS and fill the difference with
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@ -96,13 +99,11 @@ enum {
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static __must_check inline int
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RING_SPACE(struct nouveau_channel *chan, int size)
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{
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if (chan->dma.free < size) {
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int ret;
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int ret;
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ret = nouveau_dma_wait(chan, size);
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if (ret)
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return ret;
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}
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ret = nouveau_dma_wait(chan, 1, size);
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if (ret)
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return ret;
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chan->dma.free -= size;
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return 0;
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@ -146,7 +147,13 @@ FIRE_RING(struct nouveau_channel *chan)
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return;
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chan->accel_done = true;
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WRITE_PUT(chan->dma.cur);
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if (chan->dma.ib_max) {
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nv50_dma_push(chan, chan->pushbuf_bo, chan->dma.put << 2,
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chan->dma.cur - chan->dma.put);
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} else {
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WRITE_PUT(chan->dma.cur);
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}
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chan->dma.put = chan->dma.cur;
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}
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@ -239,6 +239,11 @@ struct nouveau_channel {
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int cur;
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int put;
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/* access via pushbuf_bo */
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int ib_base;
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int ib_max;
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int ib_free;
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int ib_put;
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} dma;
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uint32_t sw_subchannel[8];
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@ -848,7 +853,7 @@ nouveau_debugfs_channel_fini(struct nouveau_channel *chan)
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/* nouveau_dma.c */
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extern void nouveau_dma_pre_init(struct nouveau_channel *);
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extern int nouveau_dma_init(struct nouveau_channel *);
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extern int nouveau_dma_wait(struct nouveau_channel *, int size);
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extern int nouveau_dma_wait(struct nouveau_channel *, int slots, int size);
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/* nouveau_acpi.c */
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#ifdef CONFIG_ACPI
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@ -707,7 +707,7 @@ nouveau_gem_ioctl_pushbuf_call(struct drm_device *dev, void *data,
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uint32_t retaddy;
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if (chan->dma.free < 4 + NOUVEAU_DMA_SKIPS) {
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ret = nouveau_dma_wait(chan, 4 + NOUVEAU_DMA_SKIPS);
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ret = nouveau_dma_wait(chan, 0, 4 + NOUVEAU_DMA_SKIPS);
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if (ret) {
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NV_ERROR(dev, "jmp_space: %d\n", ret);
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goto out;
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@ -754,6 +754,15 @@ nouveau_gem_ioctl_pushbuf_call(struct drm_device *dev, void *data,
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}
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}
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if (chan->dma.ib_max) {
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ret = nouveau_dma_wait(chan, 2, 6);
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if (ret) {
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NV_INFO(dev, "nv50cal_space: %d\n", ret);
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goto out;
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}
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nv50_dma_push(chan, pbbo, req->offset, req->nr_dwords);
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} else
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if (PUSHBUF_CAL) {
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ret = RING_SPACE(chan, 2);
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if (ret) {
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@ -792,6 +801,10 @@ nouveau_gem_ioctl_pushbuf_call(struct drm_device *dev, void *data,
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kfree(bo);
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out_next:
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if (chan->dma.ib_max) {
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req->suffix0 = 0x00000000;
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req->suffix1 = 0x00000000;
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} else
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if (PUSHBUF_CAL) {
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req->suffix0 = 0x00020000;
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req->suffix1 = 0x00000000;
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@ -283,17 +283,17 @@ nv50_fifo_create_context(struct nouveau_channel *chan)
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dev_priv->engine.instmem.prepare_access(dev, true);
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nv_wo32(dev, ramfc, 0x08/4, chan->pushbuf_base);
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nv_wo32(dev, ramfc, 0x10/4, chan->pushbuf_base);
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nv_wo32(dev, ramfc, 0x48/4, chan->pushbuf->instance >> 4);
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nv_wo32(dev, ramfc, 0x80/4, (0xc << 24) | (chan->ramht->instance >> 4));
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nv_wo32(dev, ramfc, 0x3c/4, 0x00086078);
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nv_wo32(dev, ramfc, 0x44/4, 0x2101ffff);
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nv_wo32(dev, ramfc, 0x60/4, 0x7fffffff);
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nv_wo32(dev, ramfc, 0x40/4, 0x00000000);
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nv_wo32(dev, ramfc, 0x7c/4, 0x30000001);
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nv_wo32(dev, ramfc, 0x78/4, 0x00000000);
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nv_wo32(dev, ramfc, 0x4c/4, 0xffffffff);
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nv_wo32(dev, ramfc, 0x3c/4, 0x403f6078);
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nv_wo32(dev, ramfc, 0x50/4, chan->pushbuf_base +
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chan->dma.ib_base * 4);
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nv_wo32(dev, ramfc, 0x54/4, drm_order(chan->dma.ib_max + 1) << 16);
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if (!IS_G80) {
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nv_wo32(dev, chan->ramin->gpuobj, 0, chan->id);
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