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Merge patch series "Remove toolchain dependencies for Zicbom"
Conor Dooley <conor@kernel.org> says: From: Conor Dooley <conor.dooley@microchip.com> I've yoinked patch 1 from Drew's series adding support for Zicboz & attached two more patches here that remove the need for, and then drop the toolchain support checks for Zicbom. The goal is to remove the need for checking the presence of toolchain Zicbom support in the work being done to support non instruction based CMOs [1]. I've tested compliation on a number of different configurations with the Zicbom config option enabled. The important ones to call out I guess are: - clang/llvm 14 w/ LLVM=1 which doesn't support Zicbom atm. - gcc 11 w/ binutils 2.37 which doesn't support Zicbom atm either. - clang/llvm 15 w/ LLVM=1 BUT with binutils 2.37's ld. This is the configuration that prompted adding the LD checks as cc/as supports Zicbom, but ld doesn't [2]. - gcc 12 w/ binutils 2.39 & clang 15 w/ LLVM=1, both of these supported Zicbom before and still do. I also checked building the THEAD errata etc with CONFIG_RISCV_ISA_ZICBOM disabled, and there were no build issues there either. * b4-shazam-merge: RISC-V: remove toolchain version checks for Zicbom RISC-V: replace cbom instructions with an insn-def RISC-V: insn-def: Add I-type insn-def Link: https://lore.kernel.org/r/20230108163356.3063839-1-conor@kernel.org Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
This commit is contained in:
Palmer Dabbelt
commit
9a5c09dd97
4 changed files with 60 additions and 12 deletions
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@ -440,16 +440,8 @@ config RISCV_ISA_ZBB
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If you don't know what to do here, say Y.
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config TOOLCHAIN_HAS_ZICBOM
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bool
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default y
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depends on !64BIT || $(cc-option,-mabi=lp64 -march=rv64ima_zicbom)
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depends on !32BIT || $(cc-option,-mabi=ilp32 -march=rv32ima_zicbom)
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depends on LLD_VERSION >= 150000 || LD_VERSION >= 23800
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config RISCV_ISA_ZICBOM
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bool "Zicbom extension support for non-coherent DMA operation"
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depends on TOOLCHAIN_HAS_ZICBOM
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depends on !XIP_KERNEL && MMU
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default y
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select RISCV_ALTERNATIVE
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@ -58,9 +58,6 @@ riscv-march-$(CONFIG_RISCV_ISA_C) := $(riscv-march-y)c
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toolchain-need-zicsr-zifencei := $(call cc-option-yn, -march=$(riscv-march-y)_zicsr_zifencei)
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riscv-march-$(toolchain-need-zicsr-zifencei) := $(riscv-march-y)_zicsr_zifencei
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# Check if the toolchain supports Zicbom extension
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riscv-march-$(CONFIG_TOOLCHAIN_HAS_ZICBOM) := $(riscv-march-y)_zicbom
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# Check if the toolchain supports Zihintpause extension
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riscv-march-$(CONFIG_TOOLCHAIN_HAS_ZIHINTPAUSE) := $(riscv-march-y)_zihintpause
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@ -7,6 +7,7 @@
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#include <asm/alternative.h>
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#include <asm/csr.h>
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#include <asm/insn-def.h>
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#include <asm/hwcap.h>
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#include <asm/vendorid_list.h>
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@ -122,7 +123,7 @@ asm volatile(ALTERNATIVE_2( \
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"mv a0, %1\n\t" \
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"j 2f\n\t" \
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"3:\n\t" \
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"cbo." __stringify(_op) " (a0)\n\t" \
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CBO_##_op(a0) \
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"add a0, a0, %0\n\t" \
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"2:\n\t" \
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"bltu a0, %2, 3b\n\t" \
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@ -12,6 +12,12 @@
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#define INSN_R_RD_SHIFT 7
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#define INSN_R_OPCODE_SHIFT 0
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#define INSN_I_SIMM12_SHIFT 20
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#define INSN_I_RS1_SHIFT 15
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#define INSN_I_FUNC3_SHIFT 12
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#define INSN_I_RD_SHIFT 7
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#define INSN_I_OPCODE_SHIFT 0
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#ifdef __ASSEMBLY__
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#ifdef CONFIG_AS_HAS_INSN
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@ -20,6 +26,10 @@
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.insn r \opcode, \func3, \func7, \rd, \rs1, \rs2
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.endm
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.macro insn_i, opcode, func3, rd, rs1, simm12
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.insn i \opcode, \func3, \rd, \rs1, \simm12
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.endm
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#else
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#include <asm/gpr-num.h>
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@ -33,9 +43,18 @@
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(.L__gpr_num_\rs2 << INSN_R_RS2_SHIFT))
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.endm
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.macro insn_i, opcode, func3, rd, rs1, simm12
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.4byte ((\opcode << INSN_I_OPCODE_SHIFT) | \
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(\func3 << INSN_I_FUNC3_SHIFT) | \
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(.L__gpr_num_\rd << INSN_I_RD_SHIFT) | \
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(.L__gpr_num_\rs1 << INSN_I_RS1_SHIFT) | \
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(\simm12 << INSN_I_SIMM12_SHIFT))
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.endm
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#endif
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#define __INSN_R(...) insn_r __VA_ARGS__
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#define __INSN_I(...) insn_i __VA_ARGS__
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#else /* ! __ASSEMBLY__ */
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@ -44,6 +63,9 @@
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#define __INSN_R(opcode, func3, func7, rd, rs1, rs2) \
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".insn r " opcode ", " func3 ", " func7 ", " rd ", " rs1 ", " rs2 "\n"
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#define __INSN_I(opcode, func3, rd, rs1, simm12) \
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".insn i " opcode ", " func3 ", " rd ", " rs1 ", " simm12 "\n"
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#else
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#include <linux/stringify.h>
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@ -60,14 +82,32 @@
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" (.L__gpr_num_\\rs2 << " __stringify(INSN_R_RS2_SHIFT) "))\n" \
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" .endm\n"
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#define DEFINE_INSN_I \
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__DEFINE_ASM_GPR_NUMS \
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" .macro insn_i, opcode, func3, rd, rs1, simm12\n" \
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" .4byte ((\\opcode << " __stringify(INSN_I_OPCODE_SHIFT) ") |" \
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" (\\func3 << " __stringify(INSN_I_FUNC3_SHIFT) ") |" \
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" (.L__gpr_num_\\rd << " __stringify(INSN_I_RD_SHIFT) ") |" \
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" (.L__gpr_num_\\rs1 << " __stringify(INSN_I_RS1_SHIFT) ") |" \
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" (\\simm12 << " __stringify(INSN_I_SIMM12_SHIFT) "))\n" \
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" .endm\n"
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#define UNDEFINE_INSN_R \
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" .purgem insn_r\n"
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#define UNDEFINE_INSN_I \
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" .purgem insn_i\n"
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#define __INSN_R(opcode, func3, func7, rd, rs1, rs2) \
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DEFINE_INSN_R \
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"insn_r " opcode ", " func3 ", " func7 ", " rd ", " rs1 ", " rs2 "\n" \
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UNDEFINE_INSN_R
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#define __INSN_I(opcode, func3, rd, rs1, simm12) \
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DEFINE_INSN_I \
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"insn_i " opcode ", " func3 ", " rd ", " rs1 ", " simm12 "\n" \
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UNDEFINE_INSN_I
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#endif
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#endif /* ! __ASSEMBLY__ */
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@ -76,9 +116,14 @@
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__INSN_R(RV_##opcode, RV_##func3, RV_##func7, \
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RV_##rd, RV_##rs1, RV_##rs2)
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#define INSN_I(opcode, func3, rd, rs1, simm12) \
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__INSN_I(RV_##opcode, RV_##func3, RV_##rd, \
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RV_##rs1, RV_##simm12)
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#define RV_OPCODE(v) __ASM_STR(v)
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#define RV_FUNC3(v) __ASM_STR(v)
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#define RV_FUNC7(v) __ASM_STR(v)
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#define RV_SIMM12(v) __ASM_STR(v)
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#define RV_RD(v) __ASM_STR(v)
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#define RV_RS1(v) __ASM_STR(v)
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#define RV_RS2(v) __ASM_STR(v)
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@ -87,6 +132,7 @@
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#define RV___RS1(v) __RV_REG(v)
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#define RV___RS2(v) __RV_REG(v)
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#define RV_OPCODE_MISC_MEM RV_OPCODE(15)
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#define RV_OPCODE_SYSTEM RV_OPCODE(115)
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#define HFENCE_VVMA(vaddr, asid) \
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@ -134,4 +180,16 @@
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INSN_R(OPCODE_SYSTEM, FUNC3(0), FUNC7(51), \
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__RD(0), RS1(gaddr), RS2(vmid))
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#define CBO_inval(base) \
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INSN_I(OPCODE_MISC_MEM, FUNC3(2), __RD(0), \
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RS1(base), SIMM12(0))
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#define CBO_clean(base) \
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INSN_I(OPCODE_MISC_MEM, FUNC3(2), __RD(0), \
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RS1(base), SIMM12(1))
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#define CBO_flush(base) \
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INSN_I(OPCODE_MISC_MEM, FUNC3(2), __RD(0), \
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RS1(base), SIMM12(2))
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#endif /* __ASM_INSN_DEF_H */
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