Merge tag 'drm-msm-fixes-2023-07-27' of https://gitlab.freedesktop.org/drm/msm into drm-fixes
Fixes for v6.5-rc4 Display: + Fix to correct the UBWC programming for decoder version 4.3 seen on SM8550 + Add the missing flush and fetch bits for DMA4 and DMA5 SSPPs. + Fix to drop the unused dpu_core_perf_data_bus_id enum from the code + Drop the unused dsi_phy_14nm_17mA_regulators from QCM 2290 DSI cfg. GPU: + Fix warn splat for newer devices without revn + Remove name/revn for a690.. we shouldn't be populating these for newer devices, for consistency, but it slipped through review + Fix a6xx gpu snapshot BINDLESS_DATA size (was listed in bytes instead of dwords, causing AHB faults on a6xx gen4/a660-family) + Disallow submit with fence id 0 Signed-off-by: Dave Airlie <airlied@redhat.com> From: Rob Clark <robdclark@gmail.com> Link: https://patchwork.freedesktop.org/patch/msgid/CAF6AEGs9MwCSfiyv8i7yWAsJKYEzCDyzaTx=ujX80Y23rZd9RA@mail.gmail.com
This commit is contained in:
commit
9a767faa94
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@ -89,7 +89,7 @@ static void a5xx_submit_in_rb(struct msm_gpu *gpu, struct msm_gem_submit *submit
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* since we've already mapped it once in
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* submit_reloc()
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*/
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if (WARN_ON(!ptr))
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if (WARN_ON(IS_ERR_OR_NULL(ptr)))
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return;
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for (i = 0; i < dwords; i++) {
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@ -206,7 +206,7 @@ static const struct a6xx_shader_block {
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SHADER(A6XX_SP_LB_3_DATA, 0x800),
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SHADER(A6XX_SP_LB_4_DATA, 0x800),
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SHADER(A6XX_SP_LB_5_DATA, 0x200),
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SHADER(A6XX_SP_CB_BINDLESS_DATA, 0x2000),
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SHADER(A6XX_SP_CB_BINDLESS_DATA, 0x800),
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SHADER(A6XX_SP_CB_LEGACY_DATA, 0x280),
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SHADER(A6XX_SP_UAV_DATA, 0x80),
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SHADER(A6XX_SP_INST_TAG, 0x80),
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@ -369,8 +369,6 @@ static const struct adreno_info gpulist[] = {
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.hwcg = a640_hwcg,
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}, {
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.rev = ADRENO_REV(6, 9, 0, ANY_ID),
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.revn = 690,
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.name = "A690",
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.fw = {
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[ADRENO_FW_SQE] = "a660_sqe.fw",
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[ADRENO_FW_GMU] = "a690_gmu.bin",
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@ -149,7 +149,8 @@ bool adreno_cmp_rev(struct adreno_rev rev1, struct adreno_rev rev2);
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static inline bool adreno_is_revn(const struct adreno_gpu *gpu, uint32_t revn)
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{
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WARN_ON_ONCE(!gpu->revn);
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/* revn can be zero, but if not is set at same time as info */
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WARN_ON_ONCE(!gpu->info);
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return gpu->revn == revn;
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}
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@ -161,14 +162,16 @@ static inline bool adreno_has_gmu_wrapper(const struct adreno_gpu *gpu)
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static inline bool adreno_is_a2xx(const struct adreno_gpu *gpu)
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{
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WARN_ON_ONCE(!gpu->revn);
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/* revn can be zero, but if not is set at same time as info */
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WARN_ON_ONCE(!gpu->info);
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return (gpu->revn < 300);
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}
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static inline bool adreno_is_a20x(const struct adreno_gpu *gpu)
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{
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WARN_ON_ONCE(!gpu->revn);
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/* revn can be zero, but if not is set at same time as info */
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WARN_ON_ONCE(!gpu->info);
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return (gpu->revn < 210);
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}
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@ -307,7 +310,8 @@ static inline int adreno_is_a680(const struct adreno_gpu *gpu)
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static inline int adreno_is_a690(const struct adreno_gpu *gpu)
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{
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return adreno_is_revn(gpu, 690);
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/* The order of args is important here to handle ANY_ID correctly */
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return adreno_cmp_rev(ADRENO_REV(6, 9, 0, ANY_ID), gpu->rev);
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};
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/* check for a615, a616, a618, a619 or any derivatives */
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@ -14,19 +14,6 @@
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#define DPU_PERF_DEFAULT_MAX_CORE_CLK_RATE 412500000
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/**
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* enum dpu_core_perf_data_bus_id - data bus identifier
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* @DPU_CORE_PERF_DATA_BUS_ID_MNOC: DPU/MNOC data bus
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* @DPU_CORE_PERF_DATA_BUS_ID_LLCC: MNOC/LLCC data bus
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* @DPU_CORE_PERF_DATA_BUS_ID_EBI: LLCC/EBI data bus
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*/
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enum dpu_core_perf_data_bus_id {
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DPU_CORE_PERF_DATA_BUS_ID_MNOC,
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DPU_CORE_PERF_DATA_BUS_ID_LLCC,
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DPU_CORE_PERF_DATA_BUS_ID_EBI,
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DPU_CORE_PERF_DATA_BUS_ID_MAX,
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};
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/**
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* struct dpu_core_perf_params - definition of performance parameters
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* @max_per_pipe_ib: maximum instantaneous bandwidth request
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@ -51,7 +51,7 @@
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static const u32 fetch_tbl[SSPP_MAX] = {CTL_INVALID_BIT, 16, 17, 18, 19,
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CTL_INVALID_BIT, CTL_INVALID_BIT, CTL_INVALID_BIT, CTL_INVALID_BIT, 0,
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1, 2, 3, CTL_INVALID_BIT, CTL_INVALID_BIT};
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1, 2, 3, 4, 5};
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static int _mixer_stages(const struct dpu_lm_cfg *mixer, int count,
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enum dpu_lm lm)
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@ -198,6 +198,12 @@ static void dpu_hw_ctl_update_pending_flush_sspp(struct dpu_hw_ctl *ctx,
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case SSPP_DMA3:
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ctx->pending_flush_mask |= BIT(25);
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break;
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case SSPP_DMA4:
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ctx->pending_flush_mask |= BIT(13);
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break;
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case SSPP_DMA5:
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ctx->pending_flush_mask |= BIT(14);
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break;
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case SSPP_CURSOR0:
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ctx->pending_flush_mask |= BIT(22);
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break;
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@ -1087,8 +1087,6 @@ const struct msm_dsi_phy_cfg dsi_phy_14nm_8953_cfgs = {
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const struct msm_dsi_phy_cfg dsi_phy_14nm_2290_cfgs = {
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.has_phy_lane = true,
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.regulator_data = dsi_phy_14nm_17mA_regulators,
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.num_regulators = ARRAY_SIZE(dsi_phy_14nm_17mA_regulators),
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.ops = {
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.enable = dsi_14nm_phy_enable,
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.disable = dsi_14nm_phy_disable,
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@ -191,6 +191,12 @@ msm_fence_init(struct dma_fence *fence, struct msm_fence_context *fctx)
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f->fctx = fctx;
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/*
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* Until this point, the fence was just some pre-allocated memory,
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* no-one should have taken a reference to it yet.
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*/
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WARN_ON(kref_read(&fence->refcount));
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dma_fence_init(&f->base, &msm_fence_ops, &fctx->spinlock,
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fctx->context, ++fctx->last_fence);
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}
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@ -86,7 +86,19 @@ void __msm_gem_submit_destroy(struct kref *kref)
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}
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dma_fence_put(submit->user_fence);
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dma_fence_put(submit->hw_fence);
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/*
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* If the submit is freed before msm_job_run(), then hw_fence is
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* just some pre-allocated memory, not a reference counted fence.
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* Once the job runs and the hw_fence is initialized, it will
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* have a refcount of at least one, since the submit holds a ref
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* to the hw_fence.
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*/
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if (kref_read(&submit->hw_fence->refcount) == 0) {
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kfree(submit->hw_fence);
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} else {
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dma_fence_put(submit->hw_fence);
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}
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put_pid(submit->pid);
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msm_submitqueue_put(submit->queue);
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@ -889,7 +901,7 @@ int msm_ioctl_gem_submit(struct drm_device *dev, void *data,
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* after the job is armed
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*/
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if ((args->flags & MSM_SUBMIT_FENCE_SN_IN) &&
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idr_find(&queue->fence_idr, args->fence)) {
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(!args->fence || idr_find(&queue->fence_idr, args->fence))) {
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spin_unlock(&queue->idr_lock);
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idr_preload_end();
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ret = -EINVAL;
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@ -189,6 +189,7 @@ static int _msm_mdss_irq_domain_add(struct msm_mdss *msm_mdss)
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#define UBWC_2_0 0x20000000
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#define UBWC_3_0 0x30000000
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#define UBWC_4_0 0x40000000
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#define UBWC_4_3 0x40030000
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static void msm_mdss_setup_ubwc_dec_20(struct msm_mdss *msm_mdss)
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{
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@ -227,7 +228,10 @@ static void msm_mdss_setup_ubwc_dec_40(struct msm_mdss *msm_mdss)
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writel_relaxed(1, msm_mdss->mmio + UBWC_CTRL_2);
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writel_relaxed(0, msm_mdss->mmio + UBWC_PREDICTION_MODE);
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} else {
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writel_relaxed(2, msm_mdss->mmio + UBWC_CTRL_2);
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if (data->ubwc_dec_version == UBWC_4_3)
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writel_relaxed(3, msm_mdss->mmio + UBWC_CTRL_2);
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else
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writel_relaxed(2, msm_mdss->mmio + UBWC_CTRL_2);
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writel_relaxed(1, msm_mdss->mmio + UBWC_PREDICTION_MODE);
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}
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}
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@ -271,6 +275,7 @@ static int msm_mdss_enable(struct msm_mdss *msm_mdss)
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msm_mdss_setup_ubwc_dec_30(msm_mdss);
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break;
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case UBWC_4_0:
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case UBWC_4_3:
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msm_mdss_setup_ubwc_dec_40(msm_mdss);
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break;
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default:
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@ -569,6 +574,16 @@ static const struct msm_mdss_data sm8250_data = {
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.macrotile_mode = 1,
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};
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static const struct msm_mdss_data sm8550_data = {
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.ubwc_version = UBWC_4_0,
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.ubwc_dec_version = UBWC_4_3,
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.ubwc_swizzle = 6,
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.ubwc_static = 1,
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/* TODO: highest_bank_bit = 2 for LP_DDR4 */
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.highest_bank_bit = 3,
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.macrotile_mode = 1,
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};
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static const struct of_device_id mdss_dt_match[] = {
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{ .compatible = "qcom,mdss" },
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{ .compatible = "qcom,msm8998-mdss" },
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@ -585,7 +600,7 @@ static const struct of_device_id mdss_dt_match[] = {
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{ .compatible = "qcom,sm8250-mdss", .data = &sm8250_data },
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{ .compatible = "qcom,sm8350-mdss", .data = &sm8250_data },
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{ .compatible = "qcom,sm8450-mdss", .data = &sm8250_data },
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{ .compatible = "qcom,sm8550-mdss", .data = &sm8250_data },
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{ .compatible = "qcom,sm8550-mdss", .data = &sm8550_data },
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{}
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};
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MODULE_DEVICE_TABLE(of, mdss_dt_match);
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