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pwm: Changes for v3.20-rc1
This contains two new drivers, one for Allwinner SoCs and the other for Imagination Technologies' Pistachio SoC. Complementing this are a couple of fixes to the Atmel HLCDC PWM and STi PWM drivers as well as minor cleanups to the core and the Tegra driver. -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iQIcBAABAgAGBQJU5EPtAAoJEN0jrNd/PrOhqRcQAJSxA7/HVzyEOSphpmysTwnh gu1++iaFw0LTJ/OcoA3i6oesmbZ+W0QhEZEflEEXuQriAT/U0scC9sKcxz3iBWc3 T1+S3V8CF3ZXjo9Tuurihf/QsfrwrMwge4CQUZfdpRjgD3yiiFx9+U6NwBNmtYix C1BhR9ybHU16LUuYWct3iS1kjwW/eGx/FLYuW46dYHjcYrAlMEXCZWFhKbgZpnl7 AF6Wap2CWBrFLuftsz6kXy/w8MMx8jZXoUpWlCOs1bY2xJTjOGjkzijs6fHTv+dU +AvjoOAzsDVEsi6QYoVrNh6XvjpG/VQuk0DKQ3/OZBrKtRLFsrDD3uB5+yYg5Liv /b6/vNNL64qKrM8677PzoprjdgInCnN2EFxass4al6l9bC7IxCHRwutz+dKSfBy7 KUqOghl1cQEPxyXly4NGo4Z4pC/S03xmghfBcgdk6yulpEnV/GXPZzzyrikFqcYQ TY03BP1nJ1fkGN42kYZYkdefUOBzybEAT2q9Zq3SgVoexkgDNa1vKo4NEHbZmjYt Kz1QT1cz/en2Cp2snLSMPsidgr9YaXB6Lrl6YlLHEtG04f0Ey3/iJpMm9VAy5dEv fDgavey1OOM5qzMJv0zaK73gE8xFSqD0sV5tbig6IW1KFoICD2+mfgAnjuB17xEm RbLSMs2uuBJ3N2oO43HR =3uQb -----END PGP SIGNATURE----- Merge tag 'pwm/for-3.20-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/thierry.reding/linux-pwm Pull pwm updates from Thierry Reding: "This contains two new drivers, one for Allwinner SoCs and the other for Imagination Technologies' Pistachio SoC. Complementing this are a couple of fixes to the Atmel HLCDC PWM and STi PWM drivers as well as minor cleanups to the core and the Tegra driver" * tag 'pwm/for-3.20-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/thierry.reding/linux-pwm: pwm: tegra: Use NSEC_PER_SEC pwm: Remove unnecessary check before of_node_put() pwm: Add device tree binding document for IMG PWM DAC pwm: Imagination Technologies PWM DAC driver pwm: sti: Maintain a bitmap of configured devices pwm: sunxi: document OF bindings pwm: Add Allwinner SoC support pwm: atmel-hlcdc: Prevent division by zero pwm: atmel-hlcdc: Depend on HAVE_CLK
This commit is contained in:
commit
9a8b2aa534
10 changed files with 704 additions and 21 deletions
24
Documentation/devicetree/bindings/pwm/img-pwm.txt
Normal file
24
Documentation/devicetree/bindings/pwm/img-pwm.txt
Normal file
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@ -0,0 +1,24 @@
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*Imagination Technologies PWM DAC driver
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Required properties:
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- compatible: Should be "img,pistachio-pwm"
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- reg: Should contain physical base address and length of pwm registers.
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- clocks: Must contain an entry for each entry in clock-names.
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See ../clock/clock-bindings.txt for details.
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- clock-names: Must include the following entries.
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- pwm: PWM operating clock.
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- sys: PWM system interface clock.
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- #pwm-cells: Should be 2. See pwm.txt in this directory for the
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description of the cells format.
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- img,cr-periph: Must contain a phandle to the peripheral control
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syscon node which contains PWM control registers.
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Example:
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pwm: pwm@18101300 {
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compatible = "img,pistachio-pwm";
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reg = <0x18101300 0x100>;
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clocks = <&pwm_clk>, <&system_clk>;
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clock-names = "pwm", "sys";
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#pwm-cells = <2>;
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img,cr-periph = <&cr_periph>;
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};
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20
Documentation/devicetree/bindings/pwm/pwm-sun4i.txt
Normal file
20
Documentation/devicetree/bindings/pwm/pwm-sun4i.txt
Normal file
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@ -0,0 +1,20 @@
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Allwinner sun4i and sun7i SoC PWM controller
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Required properties:
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- compatible: should be one of:
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- "allwinner,sun4i-a10-pwm"
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- "allwinner,sun7i-a20-pwm"
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- reg: physical base address and length of the controller's registers
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- #pwm-cells: should be 3. See pwm.txt in this directory for a description of
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the cells format.
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- clocks: From common clock binding, handle to the parent clock.
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Example:
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pwm: pwm@01c20e00 {
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compatible = "allwinner,sun7i-a20-pwm";
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reg = <0x01c20e00 0xc>;
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clocks = <&osc24M>;
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#pwm-cells = <3>;
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status = "disabled";
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};
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@ -53,6 +53,7 @@ config PWM_ATMEL
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config PWM_ATMEL_HLCDC_PWM
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tristate "Atmel HLCDC PWM support"
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depends on MFD_ATMEL_HLCDC
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depends on HAVE_CLK
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help
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Generic PWM framework driver for the PWM output of the HLCDC
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(Atmel High-end LCD Controller). This PWM output is mainly used
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@ -130,6 +131,19 @@ config PWM_FSL_FTM
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To compile this driver as a module, choose M here: the module
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will be called pwm-fsl-ftm.
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config PWM_IMG
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tristate "Imagination Technologies PWM driver"
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depends on HAS_IOMEM
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depends on MFD_SYSCON
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depends on COMMON_CLK
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depends on MIPS || COMPILE_TEST
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help
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Generic PWM framework driver for Imagination Technologies
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PWM block which supports 4 channels.
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To compile this driver as a module, choose M here: the module
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will be called pwm-img
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config PWM_IMX
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tristate "i.MX PWM support"
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depends on ARCH_MXC
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@ -283,6 +297,16 @@ config PWM_STI
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To compile this driver as a module, choose M here: the module
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will be called pwm-sti.
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config PWM_SUN4I
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tristate "Allwinner PWM support"
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depends on ARCH_SUNXI || COMPILE_TEST
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depends on HAS_IOMEM && COMMON_CLK
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help
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Generic PWM framework driver for Allwinner SoCs.
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To compile this driver as a module, choose M here: the module
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will be called pwm-sun4i.
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config PWM_TEGRA
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tristate "NVIDIA Tegra PWM support"
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depends on ARCH_TEGRA
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@ -10,6 +10,7 @@ obj-$(CONFIG_PWM_BFIN) += pwm-bfin.o
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obj-$(CONFIG_PWM_CLPS711X) += pwm-clps711x.o
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obj-$(CONFIG_PWM_EP93XX) += pwm-ep93xx.o
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obj-$(CONFIG_PWM_FSL_FTM) += pwm-fsl-ftm.o
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obj-$(CONFIG_PWM_IMG) += pwm-img.o
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obj-$(CONFIG_PWM_IMX) += pwm-imx.o
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obj-$(CONFIG_PWM_JZ4740) += pwm-jz4740.o
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obj-$(CONFIG_PWM_LP3943) += pwm-lp3943.o
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@ -26,6 +27,7 @@ obj-$(CONFIG_PWM_ROCKCHIP) += pwm-rockchip.o
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obj-$(CONFIG_PWM_SAMSUNG) += pwm-samsung.o
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obj-$(CONFIG_PWM_SPEAR) += pwm-spear.o
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obj-$(CONFIG_PWM_STI) += pwm-sti.o
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obj-$(CONFIG_PWM_SUN4I) += pwm-sun4i.o
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obj-$(CONFIG_PWM_TEGRA) += pwm-tegra.o
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obj-$(CONFIG_PWM_TIECAP) += pwm-tiecap.o
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obj-$(CONFIG_PWM_TIEHRPWM) += pwm-tiehrpwm.o
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@ -192,7 +192,7 @@ static void of_pwmchip_add(struct pwm_chip *chip)
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static void of_pwmchip_remove(struct pwm_chip *chip)
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{
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if (chip->dev && chip->dev->of_node)
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if (chip->dev)
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of_node_put(chip->dev->of_node);
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}
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|
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@ -64,6 +64,9 @@ static int atmel_hlcdc_pwm_config(struct pwm_chip *c,
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if (!chip->errata || !chip->errata->slow_clk_erratum) {
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clk_freq = clk_get_rate(new_clk);
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if (!clk_freq)
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return -EINVAL;
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clk_period_ns = (u64)NSEC_PER_SEC * 256;
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do_div(clk_period_ns, clk_freq);
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}
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@ -73,6 +76,9 @@ static int atmel_hlcdc_pwm_config(struct pwm_chip *c,
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clk_period_ns > period_ns) {
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new_clk = hlcdc->sys_clk;
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clk_freq = clk_get_rate(new_clk);
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if (!clk_freq)
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return -EINVAL;
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clk_period_ns = (u64)NSEC_PER_SEC * 256;
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do_div(clk_period_ns, clk_freq);
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}
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|
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249
drivers/pwm/pwm-img.c
Normal file
249
drivers/pwm/pwm-img.c
Normal file
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@ -0,0 +1,249 @@
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/*
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* Imagination Technologies Pulse Width Modulator driver
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*
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* Copyright (c) 2014-2015, Imagination Technologies
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*
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* Based on drivers/pwm/pwm-tegra.c, Copyright (c) 2010, NVIDIA Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License.
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*/
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/mfd/syscon.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/pwm.h>
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#include <linux/regmap.h>
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#include <linux/slab.h>
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/* PWM registers */
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#define PWM_CTRL_CFG 0x0000
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#define PWM_CTRL_CFG_NO_SUB_DIV 0
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#define PWM_CTRL_CFG_SUB_DIV0 1
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#define PWM_CTRL_CFG_SUB_DIV1 2
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#define PWM_CTRL_CFG_SUB_DIV0_DIV1 3
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#define PWM_CTRL_CFG_DIV_SHIFT(ch) ((ch) * 2 + 4)
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#define PWM_CTRL_CFG_DIV_MASK 0x3
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#define PWM_CH_CFG(ch) (0x4 + (ch) * 4)
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#define PWM_CH_CFG_TMBASE_SHIFT 0
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#define PWM_CH_CFG_DUTY_SHIFT 16
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#define PERIP_PWM_PDM_CONTROL 0x0140
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#define PERIP_PWM_PDM_CONTROL_CH_MASK 0x1
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#define PERIP_PWM_PDM_CONTROL_CH_SHIFT(ch) ((ch) * 4)
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#define MAX_TMBASE_STEPS 65536
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struct img_pwm_chip {
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struct device *dev;
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struct pwm_chip chip;
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struct clk *pwm_clk;
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struct clk *sys_clk;
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void __iomem *base;
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struct regmap *periph_regs;
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};
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static inline struct img_pwm_chip *to_img_pwm_chip(struct pwm_chip *chip)
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{
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return container_of(chip, struct img_pwm_chip, chip);
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}
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static inline void img_pwm_writel(struct img_pwm_chip *chip,
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u32 reg, u32 val)
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{
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writel(val, chip->base + reg);
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}
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static inline u32 img_pwm_readl(struct img_pwm_chip *chip,
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u32 reg)
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{
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return readl(chip->base + reg);
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}
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static int img_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
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int duty_ns, int period_ns)
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{
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u32 val, div, duty, timebase;
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unsigned long mul, output_clk_hz, input_clk_hz;
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struct img_pwm_chip *pwm_chip = to_img_pwm_chip(chip);
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input_clk_hz = clk_get_rate(pwm_chip->pwm_clk);
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output_clk_hz = DIV_ROUND_UP(NSEC_PER_SEC, period_ns);
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mul = DIV_ROUND_UP(input_clk_hz, output_clk_hz);
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if (mul <= MAX_TMBASE_STEPS) {
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div = PWM_CTRL_CFG_NO_SUB_DIV;
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timebase = DIV_ROUND_UP(mul, 1);
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} else if (mul <= MAX_TMBASE_STEPS * 8) {
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div = PWM_CTRL_CFG_SUB_DIV0;
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timebase = DIV_ROUND_UP(mul, 8);
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} else if (mul <= MAX_TMBASE_STEPS * 64) {
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div = PWM_CTRL_CFG_SUB_DIV1;
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timebase = DIV_ROUND_UP(mul, 64);
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} else if (mul <= MAX_TMBASE_STEPS * 512) {
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div = PWM_CTRL_CFG_SUB_DIV0_DIV1;
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timebase = DIV_ROUND_UP(mul, 512);
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} else if (mul > MAX_TMBASE_STEPS * 512) {
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dev_err(chip->dev,
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"failed to configure timebase steps/divider value\n");
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return -EINVAL;
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}
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|
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duty = DIV_ROUND_UP(timebase * duty_ns, period_ns);
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val = img_pwm_readl(pwm_chip, PWM_CTRL_CFG);
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val &= ~(PWM_CTRL_CFG_DIV_MASK << PWM_CTRL_CFG_DIV_SHIFT(pwm->hwpwm));
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val |= (div & PWM_CTRL_CFG_DIV_MASK) <<
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PWM_CTRL_CFG_DIV_SHIFT(pwm->hwpwm);
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img_pwm_writel(pwm_chip, PWM_CTRL_CFG, val);
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|
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val = (duty << PWM_CH_CFG_DUTY_SHIFT) |
|
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(timebase << PWM_CH_CFG_TMBASE_SHIFT);
|
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img_pwm_writel(pwm_chip, PWM_CH_CFG(pwm->hwpwm), val);
|
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|
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return 0;
|
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}
|
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|
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static int img_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
|
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{
|
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u32 val;
|
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struct img_pwm_chip *pwm_chip = to_img_pwm_chip(chip);
|
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|
||||
val = img_pwm_readl(pwm_chip, PWM_CTRL_CFG);
|
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val |= BIT(pwm->hwpwm);
|
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img_pwm_writel(pwm_chip, PWM_CTRL_CFG, val);
|
||||
|
||||
regmap_update_bits(pwm_chip->periph_regs, PERIP_PWM_PDM_CONTROL,
|
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PERIP_PWM_PDM_CONTROL_CH_MASK <<
|
||||
PERIP_PWM_PDM_CONTROL_CH_SHIFT(pwm->hwpwm), 0);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void img_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
|
||||
{
|
||||
u32 val;
|
||||
struct img_pwm_chip *pwm_chip = to_img_pwm_chip(chip);
|
||||
|
||||
val = img_pwm_readl(pwm_chip, PWM_CTRL_CFG);
|
||||
val &= ~BIT(pwm->hwpwm);
|
||||
img_pwm_writel(pwm_chip, PWM_CTRL_CFG, val);
|
||||
}
|
||||
|
||||
static const struct pwm_ops img_pwm_ops = {
|
||||
.config = img_pwm_config,
|
||||
.enable = img_pwm_enable,
|
||||
.disable = img_pwm_disable,
|
||||
.owner = THIS_MODULE,
|
||||
};
|
||||
|
||||
static int img_pwm_probe(struct platform_device *pdev)
|
||||
{
|
||||
int ret;
|
||||
struct resource *res;
|
||||
struct img_pwm_chip *pwm;
|
||||
|
||||
pwm = devm_kzalloc(&pdev->dev, sizeof(*pwm), GFP_KERNEL);
|
||||
if (!pwm)
|
||||
return -ENOMEM;
|
||||
|
||||
pwm->dev = &pdev->dev;
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
pwm->base = devm_ioremap_resource(&pdev->dev, res);
|
||||
if (IS_ERR(pwm->base))
|
||||
return PTR_ERR(pwm->base);
|
||||
|
||||
pwm->periph_regs = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
|
||||
"img,cr-periph");
|
||||
if (IS_ERR(pwm->periph_regs))
|
||||
return PTR_ERR(pwm->periph_regs);
|
||||
|
||||
pwm->sys_clk = devm_clk_get(&pdev->dev, "sys");
|
||||
if (IS_ERR(pwm->sys_clk)) {
|
||||
dev_err(&pdev->dev, "failed to get system clock\n");
|
||||
return PTR_ERR(pwm->sys_clk);
|
||||
}
|
||||
|
||||
pwm->pwm_clk = devm_clk_get(&pdev->dev, "pwm");
|
||||
if (IS_ERR(pwm->pwm_clk)) {
|
||||
dev_err(&pdev->dev, "failed to get pwm clock\n");
|
||||
return PTR_ERR(pwm->pwm_clk);
|
||||
}
|
||||
|
||||
ret = clk_prepare_enable(pwm->sys_clk);
|
||||
if (ret < 0) {
|
||||
dev_err(&pdev->dev, "could not prepare or enable sys clock\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = clk_prepare_enable(pwm->pwm_clk);
|
||||
if (ret < 0) {
|
||||
dev_err(&pdev->dev, "could not prepare or enable pwm clock\n");
|
||||
goto disable_sysclk;
|
||||
}
|
||||
|
||||
pwm->chip.dev = &pdev->dev;
|
||||
pwm->chip.ops = &img_pwm_ops;
|
||||
pwm->chip.base = -1;
|
||||
pwm->chip.npwm = 4;
|
||||
|
||||
ret = pwmchip_add(&pwm->chip);
|
||||
if (ret < 0) {
|
||||
dev_err(&pdev->dev, "pwmchip_add failed: %d\n", ret);
|
||||
goto disable_pwmclk;
|
||||
}
|
||||
|
||||
platform_set_drvdata(pdev, pwm);
|
||||
return 0;
|
||||
|
||||
disable_pwmclk:
|
||||
clk_disable_unprepare(pwm->pwm_clk);
|
||||
disable_sysclk:
|
||||
clk_disable_unprepare(pwm->sys_clk);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int img_pwm_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct img_pwm_chip *pwm_chip = platform_get_drvdata(pdev);
|
||||
u32 val;
|
||||
unsigned int i;
|
||||
|
||||
for (i = 0; i < pwm_chip->chip.npwm; i++) {
|
||||
val = img_pwm_readl(pwm_chip, PWM_CTRL_CFG);
|
||||
val &= ~BIT(i);
|
||||
img_pwm_writel(pwm_chip, PWM_CTRL_CFG, val);
|
||||
}
|
||||
|
||||
clk_disable_unprepare(pwm_chip->pwm_clk);
|
||||
clk_disable_unprepare(pwm_chip->sys_clk);
|
||||
|
||||
return pwmchip_remove(&pwm_chip->chip);
|
||||
}
|
||||
|
||||
static const struct of_device_id img_pwm_of_match[] = {
|
||||
{ .compatible = "img,pistachio-pwm", },
|
||||
{ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, img_pwm_of_match);
|
||||
|
||||
static struct platform_driver img_pwm_driver = {
|
||||
.driver = {
|
||||
.name = "img-pwm",
|
||||
.of_match_table = img_pwm_of_match,
|
||||
},
|
||||
.probe = img_pwm_probe,
|
||||
.remove = img_pwm_remove,
|
||||
};
|
||||
module_platform_driver(img_pwm_driver);
|
||||
|
||||
MODULE_AUTHOR("Sai Masarapu <Sai.Masarapu@imgtec.com>");
|
||||
MODULE_DESCRIPTION("Imagination Technologies PWM DAC driver");
|
||||
MODULE_LICENSE("GPL v2");
|
|
@ -57,6 +57,7 @@ struct sti_pwm_chip {
|
|||
struct regmap_field *pwm_int_en;
|
||||
struct pwm_chip chip;
|
||||
struct pwm_device *cur;
|
||||
unsigned long configured;
|
||||
unsigned int en_count;
|
||||
struct mutex sti_pwm_lock; /* To sync between enable/disable calls */
|
||||
void __iomem *mmio;
|
||||
|
@ -102,24 +103,6 @@ static int sti_pwm_get_prescale(struct sti_pwm_chip *pc, unsigned long period,
|
|||
return 0;
|
||||
}
|
||||
|
||||
/* Calculate the number of PWM devices configured with a period. */
|
||||
static unsigned int sti_pwm_count_configured(struct pwm_chip *chip)
|
||||
{
|
||||
struct pwm_device *pwm;
|
||||
unsigned int ncfg = 0;
|
||||
unsigned int i;
|
||||
|
||||
for (i = 0; i < chip->npwm; i++) {
|
||||
pwm = &chip->pwms[i];
|
||||
if (test_bit(PWMF_REQUESTED, &pwm->flags)) {
|
||||
if (pwm_get_period(pwm))
|
||||
ncfg++;
|
||||
}
|
||||
}
|
||||
|
||||
return ncfg;
|
||||
}
|
||||
|
||||
/*
|
||||
* For STiH4xx PWM IP, the PWM period is fixed to 256 local clock cycles.
|
||||
* The only way to change the period (apart from changing the PWM input clock)
|
||||
|
@ -141,7 +124,7 @@ static int sti_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
|
|||
unsigned int ncfg;
|
||||
bool period_same = false;
|
||||
|
||||
ncfg = sti_pwm_count_configured(chip);
|
||||
ncfg = hweight_long(pc->configured);
|
||||
if (ncfg)
|
||||
period_same = (period_ns == pwm_get_period(cur));
|
||||
|
||||
|
@ -197,6 +180,7 @@ static int sti_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
|
|||
|
||||
ret = regmap_field_write(pc->pwm_int_en, 0);
|
||||
|
||||
set_bit(pwm->hwpwm, &pc->configured);
|
||||
pc->cur = pwm;
|
||||
|
||||
dev_dbg(dev, "prescale:%u, period:%i, duty:%i, pwmvalx:%u\n",
|
||||
|
@ -254,10 +238,18 @@ static void sti_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
|
|||
mutex_unlock(&pc->sti_pwm_lock);
|
||||
}
|
||||
|
||||
static void sti_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
|
||||
{
|
||||
struct sti_pwm_chip *pc = to_sti_pwmchip(chip);
|
||||
|
||||
clear_bit(pwm->hwpwm, &pc->configured);
|
||||
}
|
||||
|
||||
static const struct pwm_ops sti_pwm_ops = {
|
||||
.config = sti_pwm_config,
|
||||
.enable = sti_pwm_enable,
|
||||
.disable = sti_pwm_disable,
|
||||
.free = sti_pwm_free,
|
||||
.owner = THIS_MODULE,
|
||||
};
|
||||
|
||||
|
|
366
drivers/pwm/pwm-sun4i.c
Normal file
366
drivers/pwm/pwm-sun4i.c
Normal file
|
@ -0,0 +1,366 @@
|
|||
/*
|
||||
* Driver for Allwinner sun4i Pulse Width Modulation Controller
|
||||
*
|
||||
* Copyright (C) 2014 Alexandre Belloni <alexandre.belloni@free-electrons.com>
|
||||
*
|
||||
* Licensed under GPLv2.
|
||||
*/
|
||||
|
||||
#include <linux/bitops.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_device.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/pwm.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/spinlock.h>
|
||||
#include <linux/time.h>
|
||||
|
||||
#define PWM_CTRL_REG 0x0
|
||||
|
||||
#define PWM_CH_PRD_BASE 0x4
|
||||
#define PWM_CH_PRD_OFFSET 0x4
|
||||
#define PWM_CH_PRD(ch) (PWM_CH_PRD_BASE + PWM_CH_PRD_OFFSET * (ch))
|
||||
|
||||
#define PWMCH_OFFSET 15
|
||||
#define PWM_PRESCAL_MASK GENMASK(3, 0)
|
||||
#define PWM_PRESCAL_OFF 0
|
||||
#define PWM_EN BIT(4)
|
||||
#define PWM_ACT_STATE BIT(5)
|
||||
#define PWM_CLK_GATING BIT(6)
|
||||
#define PWM_MODE BIT(7)
|
||||
#define PWM_PULSE BIT(8)
|
||||
#define PWM_BYPASS BIT(9)
|
||||
|
||||
#define PWM_RDY_BASE 28
|
||||
#define PWM_RDY_OFFSET 1
|
||||
#define PWM_RDY(ch) BIT(PWM_RDY_BASE + PWM_RDY_OFFSET * (ch))
|
||||
|
||||
#define PWM_PRD(prd) (((prd) - 1) << 16)
|
||||
#define PWM_PRD_MASK GENMASK(15, 0)
|
||||
|
||||
#define PWM_DTY_MASK GENMASK(15, 0)
|
||||
|
||||
#define BIT_CH(bit, chan) ((bit) << ((chan) * PWMCH_OFFSET))
|
||||
|
||||
static const u32 prescaler_table[] = {
|
||||
120,
|
||||
180,
|
||||
240,
|
||||
360,
|
||||
480,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
12000,
|
||||
24000,
|
||||
36000,
|
||||
48000,
|
||||
72000,
|
||||
0,
|
||||
0,
|
||||
0, /* Actually 1 but tested separately */
|
||||
};
|
||||
|
||||
struct sun4i_pwm_data {
|
||||
bool has_prescaler_bypass;
|
||||
bool has_rdy;
|
||||
};
|
||||
|
||||
struct sun4i_pwm_chip {
|
||||
struct pwm_chip chip;
|
||||
struct clk *clk;
|
||||
void __iomem *base;
|
||||
spinlock_t ctrl_lock;
|
||||
const struct sun4i_pwm_data *data;
|
||||
};
|
||||
|
||||
static inline struct sun4i_pwm_chip *to_sun4i_pwm_chip(struct pwm_chip *chip)
|
||||
{
|
||||
return container_of(chip, struct sun4i_pwm_chip, chip);
|
||||
}
|
||||
|
||||
static inline u32 sun4i_pwm_readl(struct sun4i_pwm_chip *chip,
|
||||
unsigned long offset)
|
||||
{
|
||||
return readl(chip->base + offset);
|
||||
}
|
||||
|
||||
static inline void sun4i_pwm_writel(struct sun4i_pwm_chip *chip,
|
||||
u32 val, unsigned long offset)
|
||||
{
|
||||
writel(val, chip->base + offset);
|
||||
}
|
||||
|
||||
static int sun4i_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
|
||||
int duty_ns, int period_ns)
|
||||
{
|
||||
struct sun4i_pwm_chip *sun4i_pwm = to_sun4i_pwm_chip(chip);
|
||||
u32 prd, dty, val, clk_gate;
|
||||
u64 clk_rate, div = 0;
|
||||
unsigned int prescaler = 0;
|
||||
int err;
|
||||
|
||||
clk_rate = clk_get_rate(sun4i_pwm->clk);
|
||||
|
||||
if (sun4i_pwm->data->has_prescaler_bypass) {
|
||||
/* First, test without any prescaler when available */
|
||||
prescaler = PWM_PRESCAL_MASK;
|
||||
/*
|
||||
* When not using any prescaler, the clock period in nanoseconds
|
||||
* is not an integer so round it half up instead of
|
||||
* truncating to get less surprising values.
|
||||
*/
|
||||
div = clk_rate * period_ns + NSEC_PER_SEC/2;
|
||||
do_div(div, NSEC_PER_SEC);
|
||||
if (div - 1 > PWM_PRD_MASK)
|
||||
prescaler = 0;
|
||||
}
|
||||
|
||||
if (prescaler == 0) {
|
||||
/* Go up from the first divider */
|
||||
for (prescaler = 0; prescaler < PWM_PRESCAL_MASK; prescaler++) {
|
||||
if (!prescaler_table[prescaler])
|
||||
continue;
|
||||
div = clk_rate;
|
||||
do_div(div, prescaler_table[prescaler]);
|
||||
div = div * period_ns;
|
||||
do_div(div, NSEC_PER_SEC);
|
||||
if (div - 1 <= PWM_PRD_MASK)
|
||||
break;
|
||||
}
|
||||
|
||||
if (div - 1 > PWM_PRD_MASK) {
|
||||
dev_err(chip->dev, "period exceeds the maximum value\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
}
|
||||
|
||||
prd = div;
|
||||
div *= duty_ns;
|
||||
do_div(div, period_ns);
|
||||
dty = div;
|
||||
|
||||
err = clk_prepare_enable(sun4i_pwm->clk);
|
||||
if (err) {
|
||||
dev_err(chip->dev, "failed to enable PWM clock\n");
|
||||
return err;
|
||||
}
|
||||
|
||||
spin_lock(&sun4i_pwm->ctrl_lock);
|
||||
val = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
|
||||
|
||||
if (sun4i_pwm->data->has_rdy && (val & PWM_RDY(pwm->hwpwm))) {
|
||||
spin_unlock(&sun4i_pwm->ctrl_lock);
|
||||
clk_disable_unprepare(sun4i_pwm->clk);
|
||||
return -EBUSY;
|
||||
}
|
||||
|
||||
clk_gate = val & BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
|
||||
if (clk_gate) {
|
||||
val &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
|
||||
sun4i_pwm_writel(sun4i_pwm, val, PWM_CTRL_REG);
|
||||
}
|
||||
|
||||
val = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
|
||||
val &= ~BIT_CH(PWM_PRESCAL_MASK, pwm->hwpwm);
|
||||
val |= BIT_CH(prescaler, pwm->hwpwm);
|
||||
sun4i_pwm_writel(sun4i_pwm, val, PWM_CTRL_REG);
|
||||
|
||||
val = (dty & PWM_DTY_MASK) | PWM_PRD(prd);
|
||||
sun4i_pwm_writel(sun4i_pwm, val, PWM_CH_PRD(pwm->hwpwm));
|
||||
|
||||
if (clk_gate) {
|
||||
val = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
|
||||
val |= clk_gate;
|
||||
sun4i_pwm_writel(sun4i_pwm, val, PWM_CTRL_REG);
|
||||
}
|
||||
|
||||
spin_unlock(&sun4i_pwm->ctrl_lock);
|
||||
clk_disable_unprepare(sun4i_pwm->clk);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int sun4i_pwm_set_polarity(struct pwm_chip *chip, struct pwm_device *pwm,
|
||||
enum pwm_polarity polarity)
|
||||
{
|
||||
struct sun4i_pwm_chip *sun4i_pwm = to_sun4i_pwm_chip(chip);
|
||||
u32 val;
|
||||
int ret;
|
||||
|
||||
ret = clk_prepare_enable(sun4i_pwm->clk);
|
||||
if (ret) {
|
||||
dev_err(chip->dev, "failed to enable PWM clock\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
spin_lock(&sun4i_pwm->ctrl_lock);
|
||||
val = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
|
||||
|
||||
if (polarity != PWM_POLARITY_NORMAL)
|
||||
val &= ~BIT_CH(PWM_ACT_STATE, pwm->hwpwm);
|
||||
else
|
||||
val |= BIT_CH(PWM_ACT_STATE, pwm->hwpwm);
|
||||
|
||||
sun4i_pwm_writel(sun4i_pwm, val, PWM_CTRL_REG);
|
||||
|
||||
spin_unlock(&sun4i_pwm->ctrl_lock);
|
||||
clk_disable_unprepare(sun4i_pwm->clk);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int sun4i_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
|
||||
{
|
||||
struct sun4i_pwm_chip *sun4i_pwm = to_sun4i_pwm_chip(chip);
|
||||
u32 val;
|
||||
int ret;
|
||||
|
||||
ret = clk_prepare_enable(sun4i_pwm->clk);
|
||||
if (ret) {
|
||||
dev_err(chip->dev, "failed to enable PWM clock\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
spin_lock(&sun4i_pwm->ctrl_lock);
|
||||
val = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
|
||||
val |= BIT_CH(PWM_EN, pwm->hwpwm);
|
||||
val |= BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
|
||||
sun4i_pwm_writel(sun4i_pwm, val, PWM_CTRL_REG);
|
||||
spin_unlock(&sun4i_pwm->ctrl_lock);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void sun4i_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
|
||||
{
|
||||
struct sun4i_pwm_chip *sun4i_pwm = to_sun4i_pwm_chip(chip);
|
||||
u32 val;
|
||||
|
||||
spin_lock(&sun4i_pwm->ctrl_lock);
|
||||
val = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
|
||||
val &= ~BIT_CH(PWM_EN, pwm->hwpwm);
|
||||
val &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
|
||||
sun4i_pwm_writel(sun4i_pwm, val, PWM_CTRL_REG);
|
||||
spin_unlock(&sun4i_pwm->ctrl_lock);
|
||||
|
||||
clk_disable_unprepare(sun4i_pwm->clk);
|
||||
}
|
||||
|
||||
static const struct pwm_ops sun4i_pwm_ops = {
|
||||
.config = sun4i_pwm_config,
|
||||
.set_polarity = sun4i_pwm_set_polarity,
|
||||
.enable = sun4i_pwm_enable,
|
||||
.disable = sun4i_pwm_disable,
|
||||
.owner = THIS_MODULE,
|
||||
};
|
||||
|
||||
static const struct sun4i_pwm_data sun4i_pwm_data_a10 = {
|
||||
.has_prescaler_bypass = false,
|
||||
.has_rdy = false,
|
||||
};
|
||||
|
||||
static const struct sun4i_pwm_data sun4i_pwm_data_a20 = {
|
||||
.has_prescaler_bypass = true,
|
||||
.has_rdy = true,
|
||||
};
|
||||
|
||||
static const struct of_device_id sun4i_pwm_dt_ids[] = {
|
||||
{
|
||||
.compatible = "allwinner,sun4i-a10-pwm",
|
||||
.data = &sun4i_pwm_data_a10,
|
||||
}, {
|
||||
.compatible = "allwinner,sun7i-a20-pwm",
|
||||
.data = &sun4i_pwm_data_a20,
|
||||
}, {
|
||||
/* sentinel */
|
||||
},
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, sun4i_pwm_dt_ids);
|
||||
|
||||
static int sun4i_pwm_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct sun4i_pwm_chip *pwm;
|
||||
struct resource *res;
|
||||
u32 val;
|
||||
int i, ret;
|
||||
const struct of_device_id *match;
|
||||
|
||||
match = of_match_device(sun4i_pwm_dt_ids, &pdev->dev);
|
||||
|
||||
pwm = devm_kzalloc(&pdev->dev, sizeof(*pwm), GFP_KERNEL);
|
||||
if (!pwm)
|
||||
return -ENOMEM;
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
pwm->base = devm_ioremap_resource(&pdev->dev, res);
|
||||
if (IS_ERR(pwm->base))
|
||||
return PTR_ERR(pwm->base);
|
||||
|
||||
pwm->clk = devm_clk_get(&pdev->dev, NULL);
|
||||
if (IS_ERR(pwm->clk))
|
||||
return PTR_ERR(pwm->clk);
|
||||
|
||||
pwm->chip.dev = &pdev->dev;
|
||||
pwm->chip.ops = &sun4i_pwm_ops;
|
||||
pwm->chip.base = -1;
|
||||
pwm->chip.npwm = 2;
|
||||
pwm->chip.can_sleep = true;
|
||||
pwm->chip.of_xlate = of_pwm_xlate_with_flags;
|
||||
pwm->chip.of_pwm_n_cells = 3;
|
||||
pwm->data = match->data;
|
||||
|
||||
spin_lock_init(&pwm->ctrl_lock);
|
||||
|
||||
ret = pwmchip_add(&pwm->chip);
|
||||
if (ret < 0) {
|
||||
dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
platform_set_drvdata(pdev, pwm);
|
||||
|
||||
ret = clk_prepare_enable(pwm->clk);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "failed to enable PWM clock\n");
|
||||
goto clk_error;
|
||||
}
|
||||
|
||||
val = sun4i_pwm_readl(pwm, PWM_CTRL_REG);
|
||||
for (i = 0; i < pwm->chip.npwm; i++)
|
||||
if (!(val & BIT_CH(PWM_ACT_STATE, i)))
|
||||
pwm->chip.pwms[i].polarity = PWM_POLARITY_INVERSED;
|
||||
clk_disable_unprepare(pwm->clk);
|
||||
|
||||
return 0;
|
||||
|
||||
clk_error:
|
||||
pwmchip_remove(&pwm->chip);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int sun4i_pwm_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct sun4i_pwm_chip *pwm = platform_get_drvdata(pdev);
|
||||
|
||||
return pwmchip_remove(&pwm->chip);
|
||||
}
|
||||
|
||||
static struct platform_driver sun4i_pwm_driver = {
|
||||
.driver = {
|
||||
.name = "sun4i-pwm",
|
||||
.of_match_table = sun4i_pwm_dt_ids,
|
||||
},
|
||||
.probe = sun4i_pwm_probe,
|
||||
.remove = sun4i_pwm_remove,
|
||||
};
|
||||
module_platform_driver(sun4i_pwm_driver);
|
||||
|
||||
MODULE_ALIAS("platform:sun4i-pwm");
|
||||
MODULE_AUTHOR("Alexandre Belloni <alexandre.belloni@free-electrons.com>");
|
||||
MODULE_DESCRIPTION("Allwinner sun4i PWM driver");
|
||||
MODULE_LICENSE("GPL v2");
|
|
@ -87,7 +87,7 @@ static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
|
|||
* cycles at the PWM clock rate will take period_ns nanoseconds.
|
||||
*/
|
||||
rate = clk_get_rate(pc->clk) >> PWM_DUTY_WIDTH;
|
||||
hz = 1000000000ul / period_ns;
|
||||
hz = NSEC_PER_SEC / period_ns;
|
||||
|
||||
rate = (rate + (hz / 2)) / hz;
|
||||
|
||||
|
|
Loading…
Reference in a new issue