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Merge branch 'perf/updates' into aarch64/for-next/core 

Merge in arm64 perf updates:

  * xgene system PMUv3 support
  * 16-bit events for ARMv8.1
This commit is contained in:
Will Deacon 2017-06-26 10:50:50 +01:00
parent bcde519e8c c0f7f7acde
commit 9ad95c46c1
4 changed files with 635 additions and 62 deletions
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2
arch/arm/kernel/perf_event_v6.c
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@ -552,7 +552,7 @@ static int armv6mpcore_pmu_init(struct arm_pmu *cpu_pmu)
return 0; return 0;
} }
static struct of_device_id armv6_pmu_of_device_ids[] = { static const struct of_device_id armv6_pmu_of_device_ids[] = {
{.compatible = "arm,arm11mpcore-pmu", .data = armv6mpcore_pmu_init}, {.compatible = "arm,arm11mpcore-pmu", .data = armv6mpcore_pmu_init},
{.compatible = "arm,arm1176-pmu", .data = armv6_1176_pmu_init}, {.compatible = "arm,arm1176-pmu", .data = armv6_1176_pmu_init},
{.compatible = "arm,arm1136-pmu", .data = armv6_1136_pmu_init}, {.compatible = "arm,arm1136-pmu", .data = armv6_1136_pmu_init},

2
arch/arm64/kernel/perf_event.c
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@ -529,7 +529,7 @@ static struct attribute_group armv8_pmuv3_events_attr_group = {
.is_visible = armv8pmu_event_attr_is_visible, .is_visible = armv8pmu_event_attr_is_visible,
}; };
PMU_FORMAT_ATTR(event, "config:0-9"); PMU_FORMAT_ATTR(event, "config:0-15");
static struct attribute *armv8_pmuv3_format_attrs[] = { static struct attribute *armv8_pmuv3_format_attrs[] = {
&format_attr_event.attr, &format_attr_event.attr,

9
drivers/perf/Kconfig
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@ -3,9 +3,10 @@
# #
menu "Performance monitor support" menu "Performance monitor support"
depends on PERF_EVENTS
config ARM_PMU config ARM_PMU
depends on PERF_EVENTS && (ARM || ARM64) depends on ARM || ARM64
bool "ARM PMU framework" bool "ARM PMU framework"
default y default y
help help
@ -18,7 +19,7 @@ config ARM_PMU_ACPI
config QCOM_L2_PMU config QCOM_L2_PMU
bool "Qualcomm Technologies L2-cache PMU" bool "Qualcomm Technologies L2-cache PMU"
depends on ARCH_QCOM && ARM64 && PERF_EVENTS && ACPI depends on ARCH_QCOM && ARM64 && ACPI
help help
Provides support for the L2 cache performance monitor unit (PMU) Provides support for the L2 cache performance monitor unit (PMU)
in Qualcomm Technologies processors. in Qualcomm Technologies processors.
@ -27,7 +28,7 @@ config QCOM_L2_PMU
config QCOM_L3_PMU config QCOM_L3_PMU
bool "Qualcomm Technologies L3-cache PMU" bool "Qualcomm Technologies L3-cache PMU"
depends on ARCH_QCOM && ARM64 && PERF_EVENTS && ACPI depends on ARCH_QCOM && ARM64 && ACPI
select QCOM_IRQ_COMBINER select QCOM_IRQ_COMBINER
help help
Provides support for the L3 cache performance monitor unit (PMU) Provides support for the L3 cache performance monitor unit (PMU)
@ -36,7 +37,7 @@ config QCOM_L3_PMU
monitoring L3 cache events. monitoring L3 cache events.
config XGENE_PMU config XGENE_PMU
depends on PERF_EVENTS && ARCH_XGENE depends on ARCH_XGENE
bool "APM X-Gene SoC PMU" bool "APM X-Gene SoC PMU"
default n default n
help help

684
drivers/perf/xgene_pmu.c
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