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arm64: arch_timer: Add workaround for ARM erratum 1188873
commit 95b861a4a6
upstream.
When running on Cortex-A76, a timer access from an AArch32 EL0
task may end up with a corrupted value or register. The workaround for
this is to trap these accesses at EL1/EL2 and execute them there.
This only affects versions r0p0, r1p0 and r2p0 of the CPU.
Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: James Morse <james.morse@arm.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
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5 changed files with 39 additions and 1 deletions
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@ -458,6 +458,18 @@ config ARM64_ERRATUM_1024718
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If unsure, say Y.
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config ARM64_ERRATUM_1188873
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bool "Cortex-A76: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result"
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default y
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help
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This option adds work arounds for ARM Cortex-A76 erratum 1188873
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Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could cause
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register corruption when accessing the timer registers from
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AArch32 userspace.
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If unsure, say Y.
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config CAVIUM_ERRATUM_22375
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bool "Cavium erratum 22375, 24313"
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default y
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@ -45,7 +45,8 @@
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#define ARM64_SSBD 25
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#define ARM64_MISMATCHED_CACHE_TYPE 26
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#define ARM64_SSBS 27
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#define ARM64_WORKAROUND_1188873 28
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#define ARM64_NCAPS 28
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#define ARM64_NCAPS 29
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#endif /* __ASM_CPUCAPS_H */
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@ -87,6 +87,7 @@
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#define ARM_CPU_PART_CORTEX_A75 0xD0A
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#define ARM_CPU_PART_CORTEX_A35 0xD04
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#define ARM_CPU_PART_CORTEX_A55 0xD05
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#define ARM_CPU_PART_CORTEX_A76 0xD0B
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#define APM_CPU_PART_POTENZA 0x000
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@ -112,6 +113,7 @@
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#define MIDR_CORTEX_A75 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A75)
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#define MIDR_CORTEX_A35 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A35)
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#define MIDR_CORTEX_A55 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A55)
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#define MIDR_CORTEX_A76 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A76)
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#define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX)
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#define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX)
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#define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX)
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@ -712,6 +712,14 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
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.matches = has_ssbd_mitigation,
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.midr_range_list = arm64_ssb_cpus,
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},
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#ifdef CONFIG_ARM64_ERRATUM_1188873
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{
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/* Cortex-A76 r0p0 to r2p0 */
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.desc = "ARM erratum 1188873",
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.capability = ARM64_WORKAROUND_1188873,
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ERRATA_MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 2, 0),
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},
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#endif
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{
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}
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};
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@ -298,6 +298,13 @@ static u64 notrace arm64_858921_read_cntvct_el0(void)
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}
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#endif
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#ifdef CONFIG_ARM64_ERRATUM_1188873
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static u64 notrace arm64_1188873_read_cntvct_el0(void)
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{
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return read_sysreg(cntvct_el0);
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}
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#endif
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#ifdef CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND
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DEFINE_PER_CPU(const struct arch_timer_erratum_workaround *,
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timer_unstable_counter_workaround);
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@ -381,6 +388,14 @@ static const struct arch_timer_erratum_workaround ool_workarounds[] = {
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.read_cntvct_el0 = arm64_858921_read_cntvct_el0,
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},
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#endif
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#ifdef CONFIG_ARM64_ERRATUM_1188873
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{
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.match_type = ate_match_local_cap_id,
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.id = (void *)ARM64_WORKAROUND_1188873,
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.desc = "ARM erratum 1188873",
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.read_cntvct_el0 = arm64_1188873_read_cntvct_el0,
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},
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#endif
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};
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typedef bool (*ate_match_fn_t)(const struct arch_timer_erratum_workaround *,
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