ARM: multiplatform changes, part 3
This is the third and final bit of the multiplatform conversion for ARMv5, finishing off OMAP1. One patch enables the common-clk interface, and the other ones does the Kconfig change. These were waiting on a few dependencies to trickle in for common-clk, and the last one of those was in the USB tree. -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmKaWBMACgkQmmx57+YA GNk3iA//ZnmE5IPwjfhfcc9mrZzB+/t0LaGvafnfjtQOsVzvOjT6Pnbg+TE8XlGO z9W289iwefsw38NCZKSsbCnPKu5w/J4kE0Jd4GAG+o1WBlxxrndpCPkOSH/GlB1j Gpm2oLjfqFO/5l4JGVxjYemO4fqvjOrt/HeyR/4+c0MQBtV/GU1zCk1Tmqdw3/fE R87Wja/PyPVos4RLzAcm0YbDHn8GYPJs4NNUw6joXxXV21T0MFXALuCz7/ziEZBF wBxr8hoQwK1hZURI0ivw9ENzUNQ2KrBRyJPPTybd5DKWWgYDGBFL8Pkdm/R7Gzt6 X5qHQLop7atgMqGIk7BiJFwP7s/31F0v5G1r76ZakppasUu0BHjjx/8OIQVcnjfT pX8VclM2ajUutaa580rzhCxB1pJCEsEQeHP/DdGD+1NZWRNe98s2bssCTFl7gWp6 41oGLWBPymV8J7R39p9SQSLwMQdCytRZF7ARpwjGhdwVSRYaT035OB3l4g5Sb5A7 TjgUvQyj7P6uXSmiqccQrNQ/YIgUM7eb4qiFfjBwzp7uDCJkSTC+wly3KIk0NFsE Q7ubaa5kt56mIGkMfcMJpuEUTDhTfwZYvB+d66/23hHteAduWzugTTktvRMD+3pH h+vTqw4HcxZtCV79l+9HKcgowlPumvHPtO47aNgUzR/oeLuxMow= =RGR6 -----END PGP SIGNATURE----- Merge tag 'arm-multiplatform-5.19-3' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull yet more ARM multiplatform updates from Arnd Bergmann: "This is the third and final bit of the multiplatform conversion for ARMv5, finishing off OMAP1. One patch enables the common-clk interface, and the other ones does the Kconfig change. These were waiting on a few dependencies to trickle in for common-clk, and the last one of those was in the USB tree" * tag 'arm-multiplatform-5.19-3' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: ARM: omap1: enable multiplatform ARM: OMAP1: clock: Convert to CCF
This commit is contained in:
Linus Torvalds
commit
9af13088ab
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@ -396,19 +396,6 @@ config ARCH_SA1100
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help
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Support for StrongARM 11x0 based boards.
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config ARCH_OMAP1
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bool "TI OMAP1"
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depends on CPU_LITTLE_ENDIAN
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select CLKSRC_MMIO
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select FORCE_PCI if PCCARD
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select GENERIC_IRQ_CHIP
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select GPIOLIB
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select HAVE_LEGACY_CLK
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select IRQ_DOMAIN
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select SPARSE_IRQ
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help
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Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
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endchoice
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menu "Multiple platform selection"
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@ -17,6 +17,9 @@ CONFIG_MODULES=y
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CONFIG_MODULE_UNLOAD=y
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CONFIG_MODULE_FORCE_UNLOAD=y
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# CONFIG_BLK_DEV_BSG is not set
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CONFIG_ARCH_MULTI_V4T=y
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CONFIG_ARCH_MULTI_V5=y
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# CONFIG_ARCH_MULTI_V7 is not set
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CONFIG_ARCH_OMAP=y
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CONFIG_ARCH_OMAP1=y
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CONFIG_OMAP_RESET_CLOCKS=y
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@ -1,4 +1,16 @@
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# SPDX-License-Identifier: GPL-2.0-only
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menuconfig ARCH_OMAP1
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bool "TI OMAP1"
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depends on ARCH_MULTI_V4T || ARCH_MULTI_V5
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depends on CPU_LITTLE_ENDIAN
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select ARCH_HAS_HOLES_MEMORYMODEL
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select ARCH_OMAP
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select CLKSRC_MMIO
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select FORCE_PCI if PCCARD
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select GPIOLIB
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help
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Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
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if ARCH_OMAP1
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menu "TI OMAP1 specific features"
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@ -6,23 +18,27 @@ menu "TI OMAP1 specific features"
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comment "OMAP Core Type"
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config ARCH_OMAP730
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depends on ARCH_MULTI_V5
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bool "OMAP730 Based System"
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select ARCH_OMAP_OTG
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select CPU_ARM926T
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select OMAP_MPU_TIMER
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config ARCH_OMAP850
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depends on ARCH_MULTI_V5
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bool "OMAP850 Based System"
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select ARCH_OMAP_OTG
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select CPU_ARM926T
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config ARCH_OMAP15XX
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depends on ARCH_MULTI_V4T
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default y
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bool "OMAP15xx Based System"
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select CPU_ARM925T
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select OMAP_MPU_TIMER
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config ARCH_OMAP16XX
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depends on ARCH_MULTI_V5
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bool "OMAP16xx Based System"
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select ARCH_OMAP_OTG
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select CPU_ARM926T
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File diff suppressed because it is too large
Load Diff
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@ -11,12 +11,11 @@
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#define __ARCH_ARM_MACH_OMAP1_CLOCK_H
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#include <linux/clk.h>
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#include <linux/list.h>
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#include <linux/clkdev.h>
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#include <linux/clk-provider.h>
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struct module;
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struct clk;
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struct omap1_clk;
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struct omap_clk {
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u16 cpu;
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@ -29,7 +28,7 @@ struct omap_clk {
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.lk = { \
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.dev_id = dev, \
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.con_id = con, \
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.clk = ck, \
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.clk_hw = ck, \
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}, \
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}
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@ -40,10 +39,6 @@ struct omap_clk {
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#define CK_16XX (1 << 3) /* 16xx, 17xx, 5912 */
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#define CK_1710 (1 << 4) /* 1710 extra for rate selection */
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/* Temporary, needed during the common clock framework conversion */
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#define __clk_get_name(clk) (clk->name)
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/**
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* struct clkops - some clock function pointers
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* @enable: fn ptr that enables the current clock in hardware
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@ -51,8 +46,8 @@ struct omap_clk {
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* @allow_idle: fn ptr that enables autoidle for the current clock in hardware
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*/
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struct clkops {
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int (*enable)(struct clk *);
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void (*disable)(struct clk *);
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int (*enable)(struct omap1_clk *clk);
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void (*disable)(struct omap1_clk *clk);
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};
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/*
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@ -65,13 +60,9 @@ struct clkops {
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#define CLOCK_NO_IDLE_PARENT (1 << 2)
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/**
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* struct clk - OMAP struct clk
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* @node: list_head connecting this clock into the full clock list
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* struct omap1_clk - OMAP1 struct clk
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* @hw: struct clk_hw for common clock framework integration
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* @ops: struct clkops * for this clock
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* @name: the name of the clock in the hardware (used in hwmod data and debug)
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* @parent: pointer to this clock's parent struct clk
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* @children: list_head connecting to the child clks' @sibling list_heads
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* @sibling: list_head connecting this clk to its parent clk's @children
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* @rate: current clock rate
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* @enable_reg: register to write to enable the clock (see @enable_bit)
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* @recalc: fn ptr that returns the clock's current rate
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@ -79,102 +70,65 @@ struct clkops {
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* @round_rate: fn ptr that can round the clock's current rate
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* @init: fn ptr to do clock-specific initialization
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* @enable_bit: bitshift to write to enable/disable the clock (see @enable_reg)
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* @usecount: number of users that have requested this clock to be enabled
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* @fixed_div: when > 0, this clock's rate is its parent's rate / @fixed_div
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* @flags: see "struct clk.flags possibilities" above
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* @rate_offset: bitshift for rate selection bitfield (OMAP1 only)
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*
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* XXX @rate_offset should probably be removed and OMAP1
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* clock code converted to use clksel.
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*
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* XXX @usecount is poorly named. It should be "enable_count" or
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* something similar. "users" in the description refers to kernel
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* code (core code or drivers) that have called clk_enable() and not
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* yet called clk_disable(); the usecount of parent clocks is also
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* incremented by the clock code when clk_enable() is called on child
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* clocks and decremented by the clock code when clk_disable() is
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* called on child clocks.
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*
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* XXX @usecount, @children, @sibling should be marked for
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* internal use only.
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*
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* @children and @sibling are used to optimize parent-to-child clock
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* tree traversals. (child-to-parent traversals use @parent.)
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*
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* XXX The notion of the clock's current rate probably needs to be
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* separated from the clock's target rate.
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*/
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struct clk {
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struct list_head node;
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struct omap1_clk {
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struct clk_hw hw;
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const struct clkops *ops;
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const char *name;
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struct clk *parent;
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struct list_head children;
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struct list_head sibling; /* node for children */
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unsigned long rate;
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void __iomem *enable_reg;
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unsigned long (*recalc)(struct clk *);
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int (*set_rate)(struct clk *, unsigned long);
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long (*round_rate)(struct clk *, unsigned long);
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void (*init)(struct clk *);
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unsigned long (*recalc)(struct omap1_clk *clk, unsigned long rate);
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int (*set_rate)(struct omap1_clk *clk, unsigned long rate,
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unsigned long p_rate);
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long (*round_rate)(struct omap1_clk *clk, unsigned long rate,
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unsigned long *p_rate);
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int (*init)(struct omap1_clk *clk);
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u8 enable_bit;
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s8 usecount;
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u8 fixed_div;
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u8 flags;
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u8 rate_offset;
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#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
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struct dentry *dent; /* For visible tree hierarchy */
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#endif
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};
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#define to_omap1_clk(_hw) container_of(_hw, struct omap1_clk, hw)
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extern void clk_preinit(struct clk *clk);
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extern int clk_register(struct clk *clk);
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extern void clk_unregister(struct clk *clk);
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extern void propagate_rate(struct clk *clk);
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extern unsigned long followparent_recalc(struct clk *clk);
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unsigned long omap_fixed_divisor_recalc(struct clk *clk);
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void propagate_rate(struct omap1_clk *clk);
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unsigned long followparent_recalc(struct omap1_clk *clk, unsigned long p_rate);
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unsigned long omap_fixed_divisor_recalc(struct omap1_clk *clk, unsigned long p_rate);
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extern const struct clkops clkops_null;
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extern struct clk dummy_ck;
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extern struct omap1_clk dummy_ck;
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int omap1_clk_init(void);
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void omap1_clk_late_init(void);
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extern int omap1_clk_enable(struct clk *clk);
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extern void omap1_clk_disable(struct clk *clk);
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extern long omap1_clk_round_rate(struct clk *clk, unsigned long rate);
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extern int omap1_clk_set_rate(struct clk *clk, unsigned long rate);
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extern unsigned long omap1_ckctl_recalc(struct clk *clk);
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extern int omap1_set_sossi_rate(struct clk *clk, unsigned long rate);
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extern unsigned long omap1_sossi_recalc(struct clk *clk);
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extern unsigned long omap1_ckctl_recalc_dsp_domain(struct clk *clk);
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extern int omap1_clk_set_rate_dsp_domain(struct clk *clk, unsigned long rate);
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extern int omap1_set_uart_rate(struct clk *clk, unsigned long rate);
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extern unsigned long omap1_uart_recalc(struct clk *clk);
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extern int omap1_set_ext_clk_rate(struct clk *clk, unsigned long rate);
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extern long omap1_round_ext_clk_rate(struct clk *clk, unsigned long rate);
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extern void omap1_init_ext_clk(struct clk *clk);
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extern int omap1_select_table_rate(struct clk *clk, unsigned long rate);
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extern long omap1_round_to_table_rate(struct clk *clk, unsigned long rate);
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extern int omap1_clk_set_rate_ckctl_arm(struct clk *clk, unsigned long rate);
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extern long omap1_clk_round_rate_ckctl_arm(struct clk *clk, unsigned long rate);
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#ifdef CONFIG_OMAP_RESET_CLOCKS
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extern void omap1_clk_disable_unused(struct clk *clk);
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#else
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#define omap1_clk_disable_unused NULL
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#endif
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unsigned long omap1_ckctl_recalc(struct omap1_clk *clk, unsigned long p_rate);
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long omap1_round_sossi_rate(struct omap1_clk *clk, unsigned long rate, unsigned long *p_rate);
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int omap1_set_sossi_rate(struct omap1_clk *clk, unsigned long rate, unsigned long p_rate);
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unsigned long omap1_sossi_recalc(struct omap1_clk *clk, unsigned long p_rate);
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unsigned long omap1_ckctl_recalc_dsp_domain(struct omap1_clk *clk, unsigned long p_rate);
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int omap1_clk_set_rate_dsp_domain(struct omap1_clk *clk, unsigned long rate,
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unsigned long p_rate);
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long omap1_round_uart_rate(struct omap1_clk *clk, unsigned long rate, unsigned long *p_rate);
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int omap1_set_uart_rate(struct omap1_clk *clk, unsigned long rate, unsigned long p_rate);
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unsigned long omap1_uart_recalc(struct omap1_clk *clk, unsigned long p_rate);
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int omap1_set_ext_clk_rate(struct omap1_clk *clk, unsigned long rate, unsigned long p_rate);
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long omap1_round_ext_clk_rate(struct omap1_clk *clk, unsigned long rate, unsigned long *p_rate);
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int omap1_init_ext_clk(struct omap1_clk *clk);
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int omap1_select_table_rate(struct omap1_clk *clk, unsigned long rate, unsigned long p_rate);
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long omap1_round_to_table_rate(struct omap1_clk *clk, unsigned long rate, unsigned long *p_rate);
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int omap1_clk_set_rate_ckctl_arm(struct omap1_clk *clk, unsigned long rate, unsigned long p_rate);
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long omap1_clk_round_rate_ckctl_arm(struct omap1_clk *clk, unsigned long rate,
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unsigned long *p_rate);
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struct uart_clk {
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struct clk clk;
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unsigned long sysc_addr;
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struct omap1_clk clk;
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unsigned long sysc_addr;
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};
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/* Provide a method for preventing idling some ARM IDLECT clocks */
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struct arm_idlect1_clk {
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struct clk clk;
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unsigned long no_idle_count;
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__u8 idlect_shift;
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struct omap1_clk clk;
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unsigned long no_idle_count;
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__u8 idlect_shift;
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};
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/* ARM_CKCTL bit shifts */
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@ -224,7 +178,7 @@ struct arm_idlect1_clk {
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#define SOFT_REQ_REG2 0xfffe0880
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extern __u32 arm_idlect1_mask;
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extern struct clk *api_ck_p, *ck_dpll1_p, *ck_ref_p;
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extern struct omap1_clk *api_ck_p, *ck_dpll1_p, *ck_ref_p;
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extern const struct clkops clkops_dspck;
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extern const struct clkops clkops_uart_16xx;
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@ -233,4 +187,9 @@ extern const struct clkops clkops_generic;
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/* used for passing SoC type to omap1_{select,round_to}_table_rate() */
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extern u32 cpu_mask;
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|
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extern const struct clk_ops omap1_clk_null_ops;
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extern const struct clk_ops omap1_clk_gate_ops;
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extern const struct clk_ops omap1_clk_rate_ops;
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extern const struct clk_ops omap1_clk_full_ops;
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|
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#endif
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|
|
|
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@ -14,6 +14,8 @@
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#include <linux/kernel.h>
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#include <linux/io.h>
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#include <linux/clk.h>
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#include <linux/clkdev.h>
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#include <linux/clk-provider.h>
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#include <linux/cpufreq.h>
|
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#include <linux/delay.h>
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#include <linux/soc/ti/omap1-io.h>
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|
|
@ -71,16 +73,18 @@
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* Omap1 clocks
|
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*/
|
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static struct clk ck_ref = {
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.name = "ck_ref",
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.ops = &clkops_null,
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static struct omap1_clk ck_ref = {
|
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.hw.init = CLK_HW_INIT_NO_PARENT("ck_ref", &omap1_clk_rate_ops, 0),
|
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.rate = 12000000,
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};
|
||||
|
||||
static struct clk ck_dpll1 = {
|
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.name = "ck_dpll1",
|
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.ops = &clkops_null,
|
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.parent = &ck_ref,
|
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static struct omap1_clk ck_dpll1 = {
|
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.hw.init = CLK_HW_INIT("ck_dpll1", "ck_ref", &omap1_clk_rate_ops,
|
||||
/*
|
||||
* force recursive refresh of rates of the clock
|
||||
* and its children when clk_get_rate() is called
|
||||
*/
|
||||
CLK_GET_RATE_NOCACHE),
|
||||
};
|
||||
|
||||
/*
|
||||
|
|
@ -89,32 +93,28 @@ static struct clk ck_dpll1 = {
|
|||
*/
|
||||
static struct arm_idlect1_clk ck_dpll1out = {
|
||||
.clk = {
|
||||
.name = "ck_dpll1out",
|
||||
.hw.init = CLK_HW_INIT("ck_dpll1out", "ck_dpll1", &omap1_clk_gate_ops, 0),
|
||||
.ops = &clkops_generic,
|
||||
.parent = &ck_dpll1,
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||||
.flags = CLOCK_IDLE_CONTROL | ENABLE_REG_32BIT,
|
||||
.enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
|
||||
.enable_bit = EN_CKOUT_ARM,
|
||||
.recalc = &followparent_recalc,
|
||||
},
|
||||
.idlect_shift = IDL_CLKOUT_ARM_SHIFT,
|
||||
};
|
||||
|
||||
static struct clk sossi_ck = {
|
||||
.name = "ck_sossi",
|
||||
static struct omap1_clk sossi_ck = {
|
||||
.hw.init = CLK_HW_INIT("ck_sossi", "ck_dpll1out", &omap1_clk_full_ops, 0),
|
||||
.ops = &clkops_generic,
|
||||
.parent = &ck_dpll1out.clk,
|
||||
.flags = CLOCK_NO_IDLE_PARENT | ENABLE_REG_32BIT,
|
||||
.enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_1),
|
||||
.enable_bit = CONF_MOD_SOSSI_CLK_EN_R,
|
||||
.recalc = &omap1_sossi_recalc,
|
||||
.round_rate = &omap1_round_sossi_rate,
|
||||
.set_rate = &omap1_set_sossi_rate,
|
||||
};
|
||||
|
||||
static struct clk arm_ck = {
|
||||
.name = "arm_ck",
|
||||
.ops = &clkops_null,
|
||||
.parent = &ck_dpll1,
|
||||
static struct omap1_clk arm_ck = {
|
||||
.hw.init = CLK_HW_INIT("arm_ck", "ck_dpll1", &omap1_clk_rate_ops, 0),
|
||||
.rate_offset = CKCTL_ARMDIV_OFFSET,
|
||||
.recalc = &omap1_ckctl_recalc,
|
||||
.round_rate = omap1_clk_round_rate_ckctl_arm,
|
||||
|
|
@ -123,9 +123,9 @@ static struct clk arm_ck = {
|
|||
|
||||
static struct arm_idlect1_clk armper_ck = {
|
||||
.clk = {
|
||||
.name = "armper_ck",
|
||||
.hw.init = CLK_HW_INIT("armper_ck", "ck_dpll1", &omap1_clk_full_ops,
|
||||
CLK_IS_CRITICAL),
|
||||
.ops = &clkops_generic,
|
||||
.parent = &ck_dpll1,
|
||||
.flags = CLOCK_IDLE_CONTROL,
|
||||
.enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
|
||||
.enable_bit = EN_PERCK,
|
||||
|
|
@ -141,46 +141,41 @@ static struct arm_idlect1_clk armper_ck = {
|
|||
* FIXME: This clock seems to be necessary but no-one has asked for its
|
||||
* activation. [ GPIO code for 1510 ]
|
||||
*/
|
||||
static struct clk arm_gpio_ck = {
|
||||
.name = "ick",
|
||||
static struct omap1_clk arm_gpio_ck = {
|
||||
.hw.init = CLK_HW_INIT("ick", "ck_dpll1", &omap1_clk_gate_ops, CLK_IS_CRITICAL),
|
||||
.ops = &clkops_generic,
|
||||
.parent = &ck_dpll1,
|
||||
.enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
|
||||
.enable_bit = EN_GPIOCK,
|
||||
.recalc = &followparent_recalc,
|
||||
};
|
||||
|
||||
static struct arm_idlect1_clk armxor_ck = {
|
||||
.clk = {
|
||||
.name = "armxor_ck",
|
||||
.hw.init = CLK_HW_INIT("armxor_ck", "ck_ref", &omap1_clk_gate_ops,
|
||||
CLK_IS_CRITICAL),
|
||||
.ops = &clkops_generic,
|
||||
.parent = &ck_ref,
|
||||
.flags = CLOCK_IDLE_CONTROL,
|
||||
.enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
|
||||
.enable_bit = EN_XORPCK,
|
||||
.recalc = &followparent_recalc,
|
||||
},
|
||||
.idlect_shift = IDLXORP_ARM_SHIFT,
|
||||
};
|
||||
|
||||
static struct arm_idlect1_clk armtim_ck = {
|
||||
.clk = {
|
||||
.name = "armtim_ck",
|
||||
.hw.init = CLK_HW_INIT("armtim_ck", "ck_ref", &omap1_clk_gate_ops,
|
||||
CLK_IS_CRITICAL),
|
||||
.ops = &clkops_generic,
|
||||
.parent = &ck_ref,
|
||||
.flags = CLOCK_IDLE_CONTROL,
|
||||
.enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
|
||||
.enable_bit = EN_TIMCK,
|
||||
.recalc = &followparent_recalc,
|
||||
},
|
||||
.idlect_shift = IDLTIM_ARM_SHIFT,
|
||||
};
|
||||
|
||||
static struct arm_idlect1_clk armwdt_ck = {
|
||||
.clk = {
|
||||
.name = "armwdt_ck",
|
||||
.hw.init = CLK_HW_INIT("armwdt_ck", "ck_ref", &omap1_clk_full_ops, 0),
|
||||
.ops = &clkops_generic,
|
||||
.parent = &ck_ref,
|
||||
.flags = CLOCK_IDLE_CONTROL,
|
||||
.enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
|
||||
.enable_bit = EN_WDTCK,
|
||||
|
|
@ -190,11 +185,8 @@ static struct arm_idlect1_clk armwdt_ck = {
|
|||
.idlect_shift = IDLWDT_ARM_SHIFT,
|
||||
};
|
||||
|
||||
static struct clk arminth_ck16xx = {
|
||||
.name = "arminth_ck",
|
||||
.ops = &clkops_null,
|
||||
.parent = &arm_ck,
|
||||
.recalc = &followparent_recalc,
|
||||
static struct omap1_clk arminth_ck16xx = {
|
||||
.hw.init = CLK_HW_INIT("arminth_ck", "arm_ck", &omap1_clk_null_ops, 0),
|
||||
/* Note: On 16xx the frequency can be divided by 2 by programming
|
||||
* ARM_CKCTL:ARM_INTHCK_SEL(14) to 1
|
||||
*
|
||||
|
|
@ -202,10 +194,9 @@ static struct clk arminth_ck16xx = {
|
|||
*/
|
||||
};
|
||||
|
||||
static struct clk dsp_ck = {
|
||||
.name = "dsp_ck",
|
||||
static struct omap1_clk dsp_ck = {
|
||||
.hw.init = CLK_HW_INIT("dsp_ck", "ck_dpll1", &omap1_clk_full_ops, 0),
|
||||
.ops = &clkops_generic,
|
||||
.parent = &ck_dpll1,
|
||||
.enable_reg = OMAP1_IO_ADDRESS(ARM_CKCTL),
|
||||
.enable_bit = EN_DSPCK,
|
||||
.rate_offset = CKCTL_DSPDIV_OFFSET,
|
||||
|
|
@ -214,20 +205,17 @@ static struct clk dsp_ck = {
|
|||
.set_rate = omap1_clk_set_rate_ckctl_arm,
|
||||
};
|
||||
|
||||
static struct clk dspmmu_ck = {
|
||||
.name = "dspmmu_ck",
|
||||
.ops = &clkops_null,
|
||||
.parent = &ck_dpll1,
|
||||
static struct omap1_clk dspmmu_ck = {
|
||||
.hw.init = CLK_HW_INIT("dspmmu_ck", "ck_dpll1", &omap1_clk_rate_ops, 0),
|
||||
.rate_offset = CKCTL_DSPMMUDIV_OFFSET,
|
||||
.recalc = &omap1_ckctl_recalc,
|
||||
.round_rate = omap1_clk_round_rate_ckctl_arm,
|
||||
.set_rate = omap1_clk_set_rate_ckctl_arm,
|
||||
};
|
||||
|
||||
static struct clk dspper_ck = {
|
||||
.name = "dspper_ck",
|
||||
static struct omap1_clk dspper_ck = {
|
||||
.hw.init = CLK_HW_INIT("dspper_ck", "ck_dpll1", &omap1_clk_full_ops, 0),
|
||||
.ops = &clkops_dspck,
|
||||
.parent = &ck_dpll1,
|
||||
.enable_reg = DSP_IDLECT2,
|
||||
.enable_bit = EN_PERCK,
|
||||
.rate_offset = CKCTL_PERDIV_OFFSET,
|
||||
|
|
@ -236,29 +224,23 @@ static struct clk dspper_ck = {
|
|||
.set_rate = &omap1_clk_set_rate_dsp_domain,
|
||||
};
|
||||
|
||||
static struct clk dspxor_ck = {
|
||||
.name = "dspxor_ck",
|
||||
static struct omap1_clk dspxor_ck = {
|
||||
.hw.init = CLK_HW_INIT("dspxor_ck", "ck_ref", &omap1_clk_gate_ops, 0),
|
||||
.ops = &clkops_dspck,
|
||||
.parent = &ck_ref,
|
||||
.enable_reg = DSP_IDLECT2,
|
||||
.enable_bit = EN_XORPCK,
|
||||
.recalc = &followparent_recalc,
|
||||
};
|
||||
|
||||
static struct clk dsptim_ck = {
|
||||
.name = "dsptim_ck",
|
||||
static struct omap1_clk dsptim_ck = {
|
||||
.hw.init = CLK_HW_INIT("dsptim_ck", "ck_ref", &omap1_clk_gate_ops, 0),
|
||||
.ops = &clkops_dspck,
|
||||
.parent = &ck_ref,
|
||||
.enable_reg = DSP_IDLECT2,
|
||||
.enable_bit = EN_DSPTIMCK,
|
||||
.recalc = &followparent_recalc,
|
||||
};
|
||||
|
||||
static struct arm_idlect1_clk tc_ck = {
|
||||
.clk = {
|
||||
.name = "tc_ck",
|
||||
.ops = &clkops_null,
|
||||
.parent = &ck_dpll1,
|
||||
.hw.init = CLK_HW_INIT("tc_ck", "ck_dpll1", &omap1_clk_rate_ops, 0),
|
||||
.flags = CLOCK_IDLE_CONTROL,
|
||||
.rate_offset = CKCTL_TCDIV_OFFSET,
|
||||
.recalc = &omap1_ckctl_recalc,
|
||||
|
|
@ -268,116 +250,88 @@ static struct arm_idlect1_clk tc_ck = {
|
|||
.idlect_shift = IDLIF_ARM_SHIFT,
|
||||
};
|
||||
|
||||
static struct clk arminth_ck1510 = {
|
||||
.name = "arminth_ck",
|
||||
.ops = &clkops_null,
|
||||
.parent = &tc_ck.clk,
|
||||
.recalc = &followparent_recalc,
|
||||
static struct omap1_clk arminth_ck1510 = {
|
||||
.hw.init = CLK_HW_INIT("arminth_ck", "tc_ck", &omap1_clk_null_ops, 0),
|
||||
/* Note: On 1510 the frequency follows TC_CK
|
||||
*
|
||||
* 16xx version is in MPU clocks.
|
||||
*/
|
||||
};
|
||||
|
||||
static struct clk tipb_ck = {
|
||||
static struct omap1_clk tipb_ck = {
|
||||
/* No-idle controlled by "tc_ck" */
|
||||
.name = "tipb_ck",
|
||||
.ops = &clkops_null,
|
||||
.parent = &tc_ck.clk,
|
||||
.recalc = &followparent_recalc,
|
||||
.hw.init = CLK_HW_INIT("tipb_ck", "tc_ck", &omap1_clk_null_ops, 0),
|
||||
};
|
||||
|
||||
static struct clk l3_ocpi_ck = {
|
||||
static struct omap1_clk l3_ocpi_ck = {
|
||||
/* No-idle controlled by "tc_ck" */
|
||||
.name = "l3_ocpi_ck",
|
||||
.hw.init = CLK_HW_INIT("l3_ocpi_ck", "tc_ck", &omap1_clk_gate_ops, 0),
|
||||
.ops = &clkops_generic,
|
||||
.parent = &tc_ck.clk,
|
||||
.enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3),
|
||||
.enable_bit = EN_OCPI_CK,
|
||||
.recalc = &followparent_recalc,
|
||||
};
|
||||
|
||||
static struct clk tc1_ck = {
|
||||
.name = "tc1_ck",
|
||||
static struct omap1_clk tc1_ck = {
|
||||
.hw.init = CLK_HW_INIT("tc1_ck", "tc_ck", &omap1_clk_gate_ops, 0),
|
||||
.ops = &clkops_generic,
|
||||
.parent = &tc_ck.clk,
|
||||
.enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3),
|
||||
.enable_bit = EN_TC1_CK,
|
||||
.recalc = &followparent_recalc,
|
||||
};
|
||||
|
||||
/*
|
||||
* FIXME: This clock seems to be necessary but no-one has asked for its
|
||||
* activation. [ pm.c (SRAM), CCP, Camera ]
|
||||
*/
|
||||
static struct clk tc2_ck = {
|
||||
.name = "tc2_ck",
|
||||
|
||||
static struct omap1_clk tc2_ck = {
|
||||
.hw.init = CLK_HW_INIT("tc2_ck", "tc_ck", &omap1_clk_gate_ops, CLK_IS_CRITICAL),
|
||||
.ops = &clkops_generic,
|
||||
.parent = &tc_ck.clk,
|
||||
.enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3),
|
||||
.enable_bit = EN_TC2_CK,
|
||||
.recalc = &followparent_recalc,
|
||||
};
|
||||
|
||||
static struct clk dma_ck = {
|
||||
static struct omap1_clk dma_ck = {
|
||||
/* No-idle controlled by "tc_ck" */
|
||||
.name = "dma_ck",
|
||||
.ops = &clkops_null,
|
||||
.parent = &tc_ck.clk,
|
||||
.recalc = &followparent_recalc,
|
||||
.hw.init = CLK_HW_INIT("dma_ck", "tc_ck", &omap1_clk_null_ops, 0),
|
||||
};
|
||||
|
||||
static struct clk dma_lcdfree_ck = {
|
||||
.name = "dma_lcdfree_ck",
|
||||
.ops = &clkops_null,
|
||||
.parent = &tc_ck.clk,
|
||||
.recalc = &followparent_recalc,
|
||||
static struct omap1_clk dma_lcdfree_ck = {
|
||||
.hw.init = CLK_HW_INIT("dma_lcdfree_ck", "tc_ck", &omap1_clk_null_ops, 0),
|
||||
};
|
||||
|
||||
static struct arm_idlect1_clk api_ck = {
|
||||
.clk = {
|
||||
.name = "api_ck",
|
||||
.hw.init = CLK_HW_INIT("api_ck", "tc_ck", &omap1_clk_gate_ops, 0),
|
||||
.ops = &clkops_generic,
|
||||
.parent = &tc_ck.clk,
|
||||
.flags = CLOCK_IDLE_CONTROL,
|
||||
.enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
|
||||
.enable_bit = EN_APICK,
|
||||
.recalc = &followparent_recalc,
|
||||
},
|
||||
.idlect_shift = IDLAPI_ARM_SHIFT,
|
||||
};
|
||||
|
||||
static struct arm_idlect1_clk lb_ck = {
|
||||
.clk = {
|
||||
.name = "lb_ck",
|
||||
.hw.init = CLK_HW_INIT("lb_ck", "tc_ck", &omap1_clk_gate_ops, 0),
|
||||
.ops = &clkops_generic,
|
||||
.parent = &tc_ck.clk,
|
||||
.flags = CLOCK_IDLE_CONTROL,
|
||||
.enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
|
||||
.enable_bit = EN_LBCK,
|
||||
.recalc = &followparent_recalc,
|
||||
},
|
||||
.idlect_shift = IDLLB_ARM_SHIFT,
|
||||
};
|
||||
|
||||
static struct clk rhea1_ck = {
|
||||
.name = "rhea1_ck",
|
||||
.ops = &clkops_null,
|
||||
.parent = &tc_ck.clk,
|
||||
.recalc = &followparent_recalc,
|
||||
static struct omap1_clk rhea1_ck = {
|
||||
.hw.init = CLK_HW_INIT("rhea1_ck", "tc_ck", &omap1_clk_null_ops, 0),
|
||||
};
|
||||
|
||||
static struct clk rhea2_ck = {
|
||||
.name = "rhea2_ck",
|
||||
.ops = &clkops_null,
|
||||
.parent = &tc_ck.clk,
|
||||
.recalc = &followparent_recalc,
|
||||
static struct omap1_clk rhea2_ck = {
|
||||
.hw.init = CLK_HW_INIT("rhea2_ck", "tc_ck", &omap1_clk_null_ops, 0),
|
||||
};
|
||||
|
||||
static struct clk lcd_ck_16xx = {
|
||||
.name = "lcd_ck",
|
||||
static struct omap1_clk lcd_ck_16xx = {
|
||||
.hw.init = CLK_HW_INIT("lcd_ck", "ck_dpll1", &omap1_clk_full_ops, 0),
|
||||
.ops = &clkops_generic,
|
||||
.parent = &ck_dpll1,
|
||||
.enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
|
||||
.enable_bit = EN_LCDCK,
|
||||
.rate_offset = CKCTL_LCDDIV_OFFSET,
|
||||
|
|
@ -388,9 +342,8 @@ static struct clk lcd_ck_16xx = {
|
|||
|
||||
static struct arm_idlect1_clk lcd_ck_1510 = {
|
||||
.clk = {
|
||||
.name = "lcd_ck",
|
||||
.hw.init = CLK_HW_INIT("lcd_ck", "ck_dpll1", &omap1_clk_full_ops, 0),
|
||||
.ops = &clkops_generic,
|
||||
.parent = &ck_dpll1,
|
||||
.flags = CLOCK_IDLE_CONTROL,
|
||||
.enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
|
||||
.enable_bit = EN_LCDCK,
|
||||
|
|
@ -402,37 +355,35 @@ static struct arm_idlect1_clk lcd_ck_1510 = {
|
|||
.idlect_shift = OMAP1510_IDLLCD_ARM_SHIFT,
|
||||
};
|
||||
|
||||
|
||||
/*
|
||||
* XXX The enable_bit here is misused - it simply switches between 12MHz
|
||||
* and 48MHz. Reimplement with clksel.
|
||||
* and 48MHz. Reimplement with clk_mux.
|
||||
*
|
||||
* XXX does this need SYSC register handling?
|
||||
*/
|
||||
static struct clk uart1_1510 = {
|
||||
.name = "uart1_ck",
|
||||
.ops = &clkops_null,
|
||||
static struct omap1_clk uart1_1510 = {
|
||||
/* Direct from ULPD, no real parent */
|
||||
.parent = &armper_ck.clk,
|
||||
.rate = 12000000,
|
||||
.hw.init = CLK_HW_INIT("uart1_ck", "armper_ck", &omap1_clk_full_ops, 0),
|
||||
.flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
|
||||
.enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
|
||||
.enable_bit = CONF_MOD_UART1_CLK_MODE_R,
|
||||
.round_rate = &omap1_round_uart_rate,
|
||||
.set_rate = &omap1_set_uart_rate,
|
||||
.recalc = &omap1_uart_recalc,
|
||||
};
|
||||
|
||||
/*
|
||||
* XXX The enable_bit here is misused - it simply switches between 12MHz
|
||||
* and 48MHz. Reimplement with clksel.
|
||||
* and 48MHz. Reimplement with clk_mux.
|
||||
*
|
||||
* XXX SYSC register handling does not belong in the clock framework
|
||||
*/
|
||||
static struct uart_clk uart1_16xx = {
|
||||
.clk = {
|
||||
.name = "uart1_ck",
|
||||
.ops = &clkops_uart_16xx,
|
||||
/* Direct from ULPD, no real parent */
|
||||
.parent = &armper_ck.clk,
|
||||
.hw.init = CLK_HW_INIT("uart1_ck", "armper_ck", &omap1_clk_full_ops, 0),
|
||||
.rate = 48000000,
|
||||
.flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
|
||||
.enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
|
||||
|
|
@ -443,54 +394,49 @@ static struct uart_clk uart1_16xx = {
|
|||
|
||||
/*
|
||||
* XXX The enable_bit here is misused - it simply switches between 12MHz
|
||||
* and 48MHz. Reimplement with clksel.
|
||||
* and 48MHz. Reimplement with clk_mux.
|
||||
*
|
||||
* XXX does this need SYSC register handling?
|
||||
*/
|
||||
static struct clk uart2_ck = {
|
||||
.name = "uart2_ck",
|
||||
.ops = &clkops_null,
|
||||
static struct omap1_clk uart2_ck = {
|
||||
/* Direct from ULPD, no real parent */
|
||||
.parent = &armper_ck.clk,
|
||||
.rate = 12000000,
|
||||
.hw.init = CLK_HW_INIT("uart2_ck", "armper_ck", &omap1_clk_full_ops, 0),
|
||||
.flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
|
||||
.enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
|
||||
.enable_bit = CONF_MOD_UART2_CLK_MODE_R,
|
||||
.round_rate = &omap1_round_uart_rate,
|
||||
.set_rate = &omap1_set_uart_rate,
|
||||
.recalc = &omap1_uart_recalc,
|
||||
};
|
||||
|
||||
/*
|
||||
* XXX The enable_bit here is misused - it simply switches between 12MHz
|
||||
* and 48MHz. Reimplement with clksel.
|
||||
* and 48MHz. Reimplement with clk_mux.
|
||||
*
|
||||
* XXX does this need SYSC register handling?
|
||||
*/
|
||||
static struct clk uart3_1510 = {
|
||||
.name = "uart3_ck",
|
||||
.ops = &clkops_null,
|
||||
static struct omap1_clk uart3_1510 = {
|
||||
/* Direct from ULPD, no real parent */
|
||||
.parent = &armper_ck.clk,
|
||||
.rate = 12000000,
|
||||
.hw.init = CLK_HW_INIT("uart3_ck", "armper_ck", &omap1_clk_full_ops, 0),
|
||||
.flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
|
||||
.enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
|
||||
.enable_bit = CONF_MOD_UART3_CLK_MODE_R,
|
||||
.round_rate = &omap1_round_uart_rate,
|
||||
.set_rate = &omap1_set_uart_rate,
|
||||
.recalc = &omap1_uart_recalc,
|
||||
};
|
||||
|
||||
/*
|
||||
* XXX The enable_bit here is misused - it simply switches between 12MHz
|
||||
* and 48MHz. Reimplement with clksel.
|
||||
* and 48MHz. Reimplement with clk_mux.
|
||||
*
|
||||
* XXX SYSC register handling does not belong in the clock framework
|
||||
*/
|
||||
static struct uart_clk uart3_16xx = {
|
||||
.clk = {
|
||||
.name = "uart3_ck",
|
||||
.ops = &clkops_uart_16xx,
|
||||
/* Direct from ULPD, no real parent */
|
||||
.parent = &armper_ck.clk,
|
||||
.hw.init = CLK_HW_INIT("uart3_ck", "armper_ck", &omap1_clk_full_ops, 0),
|
||||
.rate = 48000000,
|
||||
.flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
|
||||
.enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
|
||||
|
|
@ -499,30 +445,30 @@ static struct uart_clk uart3_16xx = {
|
|||
.sysc_addr = 0xfffb9854,
|
||||
};
|
||||
|
||||
static struct clk usb_clko = { /* 6 MHz output on W4_USB_CLKO */
|
||||
.name = "usb_clko",
|
||||
static struct omap1_clk usb_clko = { /* 6 MHz output on W4_USB_CLKO */
|
||||
.ops = &clkops_generic,
|
||||
/* Direct from ULPD, no parent */
|
||||
.hw.init = CLK_HW_INIT_NO_PARENT("usb_clko", &omap1_clk_full_ops, 0),
|
||||
.rate = 6000000,
|
||||
.flags = ENABLE_REG_32BIT,
|
||||
.enable_reg = OMAP1_IO_ADDRESS(ULPD_CLOCK_CTRL),
|
||||
.enable_bit = USB_MCLK_EN_BIT,
|
||||
};
|
||||
|
||||
static struct clk usb_hhc_ck1510 = {
|
||||
.name = "usb_hhc_ck",
|
||||
static struct omap1_clk usb_hhc_ck1510 = {
|
||||
.ops = &clkops_generic,
|
||||
/* Direct from ULPD, no parent */
|
||||
.hw.init = CLK_HW_INIT_NO_PARENT("usb_hhc_ck", &omap1_clk_full_ops, 0),
|
||||
.rate = 48000000, /* Actually 2 clocks, 12MHz and 48MHz */
|
||||
.flags = ENABLE_REG_32BIT,
|
||||
.enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
|
||||
.enable_bit = USB_HOST_HHC_UHOST_EN,
|
||||
};
|
||||
|
||||
static struct clk usb_hhc_ck16xx = {
|
||||
.name = "usb_hhc_ck",
|
||||
static struct omap1_clk usb_hhc_ck16xx = {
|
||||
.ops = &clkops_generic,
|
||||
/* Direct from ULPD, no parent */
|
||||
.hw.init = CLK_HW_INIT_NO_PARENT("usb_hhc_ck", &omap1_clk_full_ops, 0),
|
||||
.rate = 48000000,
|
||||
/* OTG_SYSCON_2.OTG_PADEN == 0 (not 1510-compatible) */
|
||||
.flags = ENABLE_REG_32BIT,
|
||||
|
|
@ -530,46 +476,46 @@ static struct clk usb_hhc_ck16xx = {
|
|||
.enable_bit = OTG_SYSCON_2_UHOST_EN_SHIFT
|
||||
};
|
||||
|
||||
static struct clk usb_dc_ck = {
|
||||
.name = "usb_dc_ck",
|
||||
static struct omap1_clk usb_dc_ck = {
|
||||
.ops = &clkops_generic,
|
||||
/* Direct from ULPD, no parent */
|
||||
.hw.init = CLK_HW_INIT_NO_PARENT("usb_dc_ck", &omap1_clk_full_ops, 0),
|
||||
.rate = 48000000,
|
||||
.enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
|
||||
.enable_bit = SOFT_USB_OTG_DPLL_REQ_SHIFT,
|
||||
};
|
||||
|
||||
static struct clk uart1_7xx = {
|
||||
.name = "uart1_ck",
|
||||
static struct omap1_clk uart1_7xx = {
|
||||
.ops = &clkops_generic,
|
||||
/* Direct from ULPD, no parent */
|
||||
.hw.init = CLK_HW_INIT_NO_PARENT("uart1_ck", &omap1_clk_full_ops, 0),
|
||||
.rate = 12000000,
|
||||
.enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
|
||||
.enable_bit = 9,
|
||||
};
|
||||
|
||||
static struct clk uart2_7xx = {
|
||||
.name = "uart2_ck",
|
||||
static struct omap1_clk uart2_7xx = {
|
||||
.ops = &clkops_generic,
|
||||
/* Direct from ULPD, no parent */
|
||||
.hw.init = CLK_HW_INIT_NO_PARENT("uart2_ck", &omap1_clk_full_ops, 0),
|
||||
.rate = 12000000,
|
||||
.enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
|
||||
.enable_bit = 11,
|
||||
};
|
||||
|
||||
static struct clk mclk_1510 = {
|
||||
.name = "mclk",
|
||||
static struct omap1_clk mclk_1510 = {
|
||||
.ops = &clkops_generic,
|
||||
/* Direct from ULPD, no parent. May be enabled by ext hardware. */
|
||||
.hw.init = CLK_HW_INIT_NO_PARENT("mclk", &omap1_clk_full_ops, 0),
|
||||
.rate = 12000000,
|
||||
.enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
|
||||
.enable_bit = SOFT_COM_MCKO_REQ_SHIFT,
|
||||
};
|
||||
|
||||
static struct clk mclk_16xx = {
|
||||
.name = "mclk",
|
||||
static struct omap1_clk mclk_16xx = {
|
||||
.ops = &clkops_generic,
|
||||
/* Direct from ULPD, no parent. May be enabled by ext hardware. */
|
||||
.hw.init = CLK_HW_INIT_NO_PARENT("mclk", &omap1_clk_full_ops, 0),
|
||||
.enable_reg = OMAP1_IO_ADDRESS(COM_CLK_DIV_CTRL_SEL),
|
||||
.enable_bit = COM_ULPD_PLL_CLK_REQ,
|
||||
.set_rate = &omap1_set_ext_clk_rate,
|
||||
|
|
@ -577,17 +523,16 @@ static struct clk mclk_16xx = {
|
|||
.init = &omap1_init_ext_clk,
|
||||
};
|
||||
|
||||
static struct clk bclk_1510 = {
|
||||
.name = "bclk",
|
||||
.ops = &clkops_generic,
|
||||
static struct omap1_clk bclk_1510 = {
|
||||
/* Direct from ULPD, no parent. May be enabled by ext hardware. */
|
||||
.hw.init = CLK_HW_INIT_NO_PARENT("bclk", &omap1_clk_rate_ops, 0),
|
||||
.rate = 12000000,
|
||||
};
|
||||
|
||||
static struct clk bclk_16xx = {
|
||||
.name = "bclk",
|
||||
static struct omap1_clk bclk_16xx = {
|
||||
.ops = &clkops_generic,
|
||||
/* Direct from ULPD, no parent. May be enabled by ext hardware. */
|
||||
.hw.init = CLK_HW_INIT_NO_PARENT("bclk", &omap1_clk_full_ops, 0),
|
||||
.enable_reg = OMAP1_IO_ADDRESS(SWD_CLK_DIV_CTRL_SEL),
|
||||
.enable_bit = SWD_ULPD_PLL_CLK_REQ,
|
||||
.set_rate = &omap1_set_ext_clk_rate,
|
||||
|
|
@ -595,11 +540,10 @@ static struct clk bclk_16xx = {
|
|||
.init = &omap1_init_ext_clk,
|
||||
};
|
||||
|
||||
static struct clk mmc1_ck = {
|
||||
.name = "mmc1_ck",
|
||||
static struct omap1_clk mmc1_ck = {
|
||||
.ops = &clkops_generic,
|
||||
/* Functional clock is direct from ULPD, interface clock is ARMPER */
|
||||
.parent = &armper_ck.clk,
|
||||
.hw.init = CLK_HW_INIT("mmc1_ck", "armper_ck", &omap1_clk_full_ops, 0),
|
||||
.rate = 48000000,
|
||||
.flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
|
||||
.enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
|
||||
|
|
@ -610,32 +554,29 @@ static struct clk mmc1_ck = {
|
|||
* XXX MOD_CONF_CTRL_0 bit 20 is defined in the 1510 TRM as
|
||||
* CONF_MOD_MCBSP3_AUXON ??
|
||||
*/
|
||||
static struct clk mmc2_ck = {
|
||||
.name = "mmc2_ck",
|
||||
static struct omap1_clk mmc2_ck = {
|
||||
.ops = &clkops_generic,
|
||||
/* Functional clock is direct from ULPD, interface clock is ARMPER */
|
||||
.parent = &armper_ck.clk,
|
||||
.hw.init = CLK_HW_INIT("mmc2_ck", "armper_ck", &omap1_clk_full_ops, 0),
|
||||
.rate = 48000000,
|
||||
.flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
|
||||
.enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
|
||||
.enable_bit = 20,
|
||||
};
|
||||
|
||||
static struct clk mmc3_ck = {
|
||||
.name = "mmc3_ck",
|
||||
static struct omap1_clk mmc3_ck = {
|
||||
.ops = &clkops_generic,
|
||||
/* Functional clock is direct from ULPD, interface clock is ARMPER */
|
||||
.parent = &armper_ck.clk,
|
||||
.hw.init = CLK_HW_INIT("mmc3_ck", "armper_ck", &omap1_clk_full_ops, 0),
|
||||
.rate = 48000000,
|
||||
.flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
|
||||
.enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
|
||||
.enable_bit = SOFT_MMC_DPLL_REQ_SHIFT,
|
||||
};
|
||||
|
||||
static struct clk virtual_ck_mpu = {
|
||||
.name = "mpu",
|
||||
.ops = &clkops_null,
|
||||
.parent = &arm_ck, /* Is smarter alias for */
|
||||
static struct omap1_clk virtual_ck_mpu = {
|
||||
/* Is smarter alias for arm_ck */
|
||||
.hw.init = CLK_HW_INIT("mpu", "arm_ck", &omap1_clk_rate_ops, 0),
|
||||
.recalc = &followparent_recalc,
|
||||
.set_rate = &omap1_select_table_rate,
|
||||
.round_rate = &omap1_round_to_table_rate,
|
||||
|
|
@ -643,20 +584,14 @@ static struct clk virtual_ck_mpu = {
|
|||
|
||||
/* virtual functional clock domain for I2C. Just for making sure that ARMXOR_CK
|
||||
remains active during MPU idle whenever this is enabled */
|
||||
static struct clk i2c_fck = {
|
||||
.name = "i2c_fck",
|
||||
.ops = &clkops_null,
|
||||
static struct omap1_clk i2c_fck = {
|
||||
.hw.init = CLK_HW_INIT("i2c_fck", "armxor_ck", &omap1_clk_gate_ops, 0),
|
||||
.flags = CLOCK_NO_IDLE_PARENT,
|
||||
.parent = &armxor_ck.clk,
|
||||
.recalc = &followparent_recalc,
|
||||
};
|
||||
|
||||
static struct clk i2c_ick = {
|
||||
.name = "i2c_ick",
|
||||
.ops = &clkops_null,
|
||||
static struct omap1_clk i2c_ick = {
|
||||
.hw.init = CLK_HW_INIT("i2c_ick", "armper_ck", &omap1_clk_gate_ops, 0),
|
||||
.flags = CLOCK_NO_IDLE_PARENT,
|
||||
.parent = &armper_ck.clk,
|
||||
.recalc = &followparent_recalc,
|
||||
};
|
||||
|
||||
/*
|
||||
|
|
@ -665,81 +600,81 @@ static struct clk i2c_ick = {
|
|||
|
||||
static struct omap_clk omap_clks[] = {
|
||||
/* non-ULPD clocks */
|
||||
CLK(NULL, "ck_ref", &ck_ref, CK_16XX | CK_1510 | CK_310 | CK_7XX),
|
||||
CLK(NULL, "ck_dpll1", &ck_dpll1, CK_16XX | CK_1510 | CK_310 | CK_7XX),
|
||||
CLK(NULL, "ck_ref", &ck_ref.hw, CK_16XX | CK_1510 | CK_310 | CK_7XX),
|
||||
CLK(NULL, "ck_dpll1", &ck_dpll1.hw, CK_16XX | CK_1510 | CK_310 | CK_7XX),
|
||||
/* CK_GEN1 clocks */
|
||||
CLK(NULL, "ck_dpll1out", &ck_dpll1out.clk, CK_16XX),
|
||||
CLK(NULL, "ck_sossi", &sossi_ck, CK_16XX),
|
||||
CLK(NULL, "arm_ck", &arm_ck, CK_16XX | CK_1510 | CK_310),
|
||||
CLK(NULL, "armper_ck", &armper_ck.clk, CK_16XX | CK_1510 | CK_310),
|
||||
CLK("omap_gpio.0", "ick", &arm_gpio_ck, CK_1510 | CK_310),
|
||||
CLK(NULL, "armxor_ck", &armxor_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX),
|
||||
CLK(NULL, "armtim_ck", &armtim_ck.clk, CK_16XX | CK_1510 | CK_310),
|
||||
CLK("omap_wdt", "fck", &armwdt_ck.clk, CK_16XX | CK_1510 | CK_310),
|
||||
CLK("omap_wdt", "ick", &armper_ck.clk, CK_16XX),
|
||||
CLK("omap_wdt", "ick", &dummy_ck, CK_1510 | CK_310),
|
||||
CLK(NULL, "arminth_ck", &arminth_ck1510, CK_1510 | CK_310),
|
||||
CLK(NULL, "arminth_ck", &arminth_ck16xx, CK_16XX),
|
||||
CLK(NULL, "ck_dpll1out", &ck_dpll1out.clk.hw, CK_16XX),
|
||||
CLK(NULL, "ck_sossi", &sossi_ck.hw, CK_16XX),
|
||||
CLK(NULL, "arm_ck", &arm_ck.hw, CK_16XX | CK_1510 | CK_310),
|
||||
CLK(NULL, "armper_ck", &armper_ck.clk.hw, CK_16XX | CK_1510 | CK_310),
|
||||
CLK("omap_gpio.0", "ick", &arm_gpio_ck.hw, CK_1510 | CK_310),
|
||||
CLK(NULL, "armxor_ck", &armxor_ck.clk.hw, CK_16XX | CK_1510 | CK_310 | CK_7XX),
|
||||
CLK(NULL, "armtim_ck", &armtim_ck.clk.hw, CK_16XX | CK_1510 | CK_310),
|
||||
CLK("omap_wdt", "fck", &armwdt_ck.clk.hw, CK_16XX | CK_1510 | CK_310),
|
||||
CLK("omap_wdt", "ick", &armper_ck.clk.hw, CK_16XX),
|
||||
CLK("omap_wdt", "ick", &dummy_ck.hw, CK_1510 | CK_310),
|
||||
CLK(NULL, "arminth_ck", &arminth_ck1510.hw, CK_1510 | CK_310),
|
||||
CLK(NULL, "arminth_ck", &arminth_ck16xx.hw, CK_16XX),
|
||||
/* CK_GEN2 clocks */
|
||||
CLK(NULL, "dsp_ck", &dsp_ck, CK_16XX | CK_1510 | CK_310),
|
||||
CLK(NULL, "dspmmu_ck", &dspmmu_ck, CK_16XX | CK_1510 | CK_310),
|
||||
CLK(NULL, "dspper_ck", &dspper_ck, CK_16XX | CK_1510 | CK_310),
|
||||
CLK(NULL, "dspxor_ck", &dspxor_ck, CK_16XX | CK_1510 | CK_310),
|
||||
CLK(NULL, "dsptim_ck", &dsptim_ck, CK_16XX | CK_1510 | CK_310),
|
||||
CLK(NULL, "dsp_ck", &dsp_ck.hw, CK_16XX | CK_1510 | CK_310),
|
||||
CLK(NULL, "dspmmu_ck", &dspmmu_ck.hw, CK_16XX | CK_1510 | CK_310),
|
||||
CLK(NULL, "dspper_ck", &dspper_ck.hw, CK_16XX | CK_1510 | CK_310),
|
||||
CLK(NULL, "dspxor_ck", &dspxor_ck.hw, CK_16XX | CK_1510 | CK_310),
|
||||
CLK(NULL, "dsptim_ck", &dsptim_ck.hw, CK_16XX | CK_1510 | CK_310),
|
||||
/* CK_GEN3 clocks */
|
||||
CLK(NULL, "tc_ck", &tc_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX),
|
||||
CLK(NULL, "tipb_ck", &tipb_ck, CK_1510 | CK_310),
|
||||
CLK(NULL, "l3_ocpi_ck", &l3_ocpi_ck, CK_16XX | CK_7XX),
|
||||
CLK(NULL, "tc1_ck", &tc1_ck, CK_16XX),
|
||||
CLK(NULL, "tc2_ck", &tc2_ck, CK_16XX),
|
||||
CLK(NULL, "dma_ck", &dma_ck, CK_16XX | CK_1510 | CK_310),
|
||||
CLK(NULL, "dma_lcdfree_ck", &dma_lcdfree_ck, CK_16XX),
|
||||
CLK(NULL, "api_ck", &api_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX),
|
||||
CLK(NULL, "lb_ck", &lb_ck.clk, CK_1510 | CK_310),
|
||||
CLK(NULL, "rhea1_ck", &rhea1_ck, CK_16XX),
|
||||
CLK(NULL, "rhea2_ck", &rhea2_ck, CK_16XX),
|
||||
CLK(NULL, "lcd_ck", &lcd_ck_16xx, CK_16XX | CK_7XX),
|
||||
CLK(NULL, "lcd_ck", &lcd_ck_1510.clk, CK_1510 | CK_310),
|
||||
CLK(NULL, "tc_ck", &tc_ck.clk.hw, CK_16XX | CK_1510 | CK_310 | CK_7XX),
|
||||
CLK(NULL, "tipb_ck", &tipb_ck.hw, CK_1510 | CK_310),
|
||||
CLK(NULL, "l3_ocpi_ck", &l3_ocpi_ck.hw, CK_16XX | CK_7XX),
|
||||
CLK(NULL, "tc1_ck", &tc1_ck.hw, CK_16XX),
|
||||
CLK(NULL, "tc2_ck", &tc2_ck.hw, CK_16XX),
|
||||
CLK(NULL, "dma_ck", &dma_ck.hw, CK_16XX | CK_1510 | CK_310),
|
||||
CLK(NULL, "dma_lcdfree_ck", &dma_lcdfree_ck.hw, CK_16XX),
|
||||
CLK(NULL, "api_ck", &api_ck.clk.hw, CK_16XX | CK_1510 | CK_310 | CK_7XX),
|
||||
CLK(NULL, "lb_ck", &lb_ck.clk.hw, CK_1510 | CK_310),
|
||||
CLK(NULL, "rhea1_ck", &rhea1_ck.hw, CK_16XX),
|
||||
CLK(NULL, "rhea2_ck", &rhea2_ck.hw, CK_16XX),
|
||||
CLK(NULL, "lcd_ck", &lcd_ck_16xx.hw, CK_16XX | CK_7XX),
|
||||
CLK(NULL, "lcd_ck", &lcd_ck_1510.clk.hw, CK_1510 | CK_310),
|
||||
/* ULPD clocks */
|
||||
CLK(NULL, "uart1_ck", &uart1_1510, CK_1510 | CK_310),
|
||||
CLK(NULL, "uart1_ck", &uart1_16xx.clk, CK_16XX),
|
||||
CLK(NULL, "uart1_ck", &uart1_7xx, CK_7XX),
|
||||
CLK(NULL, "uart2_ck", &uart2_ck, CK_16XX | CK_1510 | CK_310),
|
||||
CLK(NULL, "uart2_ck", &uart2_7xx, CK_7XX),
|
||||
CLK(NULL, "uart3_ck", &uart3_1510, CK_1510 | CK_310),
|
||||
CLK(NULL, "uart3_ck", &uart3_16xx.clk, CK_16XX),
|
||||
CLK(NULL, "usb_clko", &usb_clko, CK_16XX | CK_1510 | CK_310),
|
||||
CLK(NULL, "usb_hhc_ck", &usb_hhc_ck1510, CK_1510 | CK_310),
|
||||
CLK(NULL, "usb_hhc_ck", &usb_hhc_ck16xx, CK_16XX),
|
||||
CLK(NULL, "usb_dc_ck", &usb_dc_ck, CK_16XX | CK_7XX),
|
||||
CLK(NULL, "mclk", &mclk_1510, CK_1510 | CK_310),
|
||||
CLK(NULL, "mclk", &mclk_16xx, CK_16XX),
|
||||
CLK(NULL, "bclk", &bclk_1510, CK_1510 | CK_310),
|
||||
CLK(NULL, "bclk", &bclk_16xx, CK_16XX),
|
||||
CLK("mmci-omap.0", "fck", &mmc1_ck, CK_16XX | CK_1510 | CK_310),
|
||||
CLK("mmci-omap.0", "fck", &mmc3_ck, CK_7XX),
|
||||
CLK("mmci-omap.0", "ick", &armper_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX),
|
||||
CLK("mmci-omap.1", "fck", &mmc2_ck, CK_16XX),
|
||||
CLK("mmci-omap.1", "ick", &armper_ck.clk, CK_16XX),
|
||||
CLK(NULL, "uart1_ck", &uart1_1510.hw, CK_1510 | CK_310),
|
||||
CLK(NULL, "uart1_ck", &uart1_16xx.clk.hw, CK_16XX),
|
||||
CLK(NULL, "uart1_ck", &uart1_7xx.hw, CK_7XX),
|
||||
CLK(NULL, "uart2_ck", &uart2_ck.hw, CK_16XX | CK_1510 | CK_310),
|
||||
CLK(NULL, "uart2_ck", &uart2_7xx.hw, CK_7XX),
|
||||
CLK(NULL, "uart3_ck", &uart3_1510.hw, CK_1510 | CK_310),
|
||||
CLK(NULL, "uart3_ck", &uart3_16xx.clk.hw, CK_16XX),
|
||||
CLK(NULL, "usb_clko", &usb_clko.hw, CK_16XX | CK_1510 | CK_310),
|
||||
CLK(NULL, "usb_hhc_ck", &usb_hhc_ck1510.hw, CK_1510 | CK_310),
|
||||
CLK(NULL, "usb_hhc_ck", &usb_hhc_ck16xx.hw, CK_16XX),
|
||||
CLK(NULL, "usb_dc_ck", &usb_dc_ck.hw, CK_16XX | CK_7XX),
|
||||
CLK(NULL, "mclk", &mclk_1510.hw, CK_1510 | CK_310),
|
||||
CLK(NULL, "mclk", &mclk_16xx.hw, CK_16XX),
|
||||
CLK(NULL, "bclk", &bclk_1510.hw, CK_1510 | CK_310),
|
||||
CLK(NULL, "bclk", &bclk_16xx.hw, CK_16XX),
|
||||
CLK("mmci-omap.0", "fck", &mmc1_ck.hw, CK_16XX | CK_1510 | CK_310),
|
||||
CLK("mmci-omap.0", "fck", &mmc3_ck.hw, CK_7XX),
|
||||
CLK("mmci-omap.0", "ick", &armper_ck.clk.hw, CK_16XX | CK_1510 | CK_310 | CK_7XX),
|
||||
CLK("mmci-omap.1", "fck", &mmc2_ck.hw, CK_16XX),
|
||||
CLK("mmci-omap.1", "ick", &armper_ck.clk.hw, CK_16XX),
|
||||
/* Virtual clocks */
|
||||
CLK(NULL, "mpu", &virtual_ck_mpu, CK_16XX | CK_1510 | CK_310),
|
||||
CLK("omap_i2c.1", "fck", &i2c_fck, CK_16XX | CK_1510 | CK_310 | CK_7XX),
|
||||
CLK("omap_i2c.1", "ick", &i2c_ick, CK_16XX),
|
||||
CLK("omap_i2c.1", "ick", &dummy_ck, CK_1510 | CK_310 | CK_7XX),
|
||||
CLK("omap1_spi100k.1", "fck", &dummy_ck, CK_7XX),
|
||||
CLK("omap1_spi100k.1", "ick", &dummy_ck, CK_7XX),
|
||||
CLK("omap1_spi100k.2", "fck", &dummy_ck, CK_7XX),
|
||||
CLK("omap1_spi100k.2", "ick", &dummy_ck, CK_7XX),
|
||||
CLK("omap_uwire", "fck", &armxor_ck.clk, CK_16XX | CK_1510 | CK_310),
|
||||
CLK("omap-mcbsp.1", "ick", &dspper_ck, CK_16XX),
|
||||
CLK("omap-mcbsp.1", "ick", &dummy_ck, CK_1510 | CK_310),
|
||||
CLK("omap-mcbsp.2", "ick", &armper_ck.clk, CK_16XX),
|
||||
CLK("omap-mcbsp.2", "ick", &dummy_ck, CK_1510 | CK_310),
|
||||
CLK("omap-mcbsp.3", "ick", &dspper_ck, CK_16XX),
|
||||
CLK("omap-mcbsp.3", "ick", &dummy_ck, CK_1510 | CK_310),
|
||||
CLK("omap-mcbsp.1", "fck", &dspxor_ck, CK_16XX | CK_1510 | CK_310),
|
||||
CLK("omap-mcbsp.2", "fck", &armper_ck.clk, CK_16XX | CK_1510 | CK_310),
|
||||
CLK("omap-mcbsp.3", "fck", &dspxor_ck, CK_16XX | CK_1510 | CK_310),
|
||||
CLK(NULL, "mpu", &virtual_ck_mpu.hw, CK_16XX | CK_1510 | CK_310),
|
||||
CLK("omap_i2c.1", "fck", &i2c_fck.hw, CK_16XX | CK_1510 | CK_310 | CK_7XX),
|
||||
CLK("omap_i2c.1", "ick", &i2c_ick.hw, CK_16XX),
|
||||
CLK("omap_i2c.1", "ick", &dummy_ck.hw, CK_1510 | CK_310 | CK_7XX),
|
||||
CLK("omap1_spi100k.1", "fck", &dummy_ck.hw, CK_7XX),
|
||||
CLK("omap1_spi100k.1", "ick", &dummy_ck.hw, CK_7XX),
|
||||
CLK("omap1_spi100k.2", "fck", &dummy_ck.hw, CK_7XX),
|
||||
CLK("omap1_spi100k.2", "ick", &dummy_ck.hw, CK_7XX),
|
||||
CLK("omap_uwire", "fck", &armxor_ck.clk.hw, CK_16XX | CK_1510 | CK_310),
|
||||
CLK("omap-mcbsp.1", "ick", &dspper_ck.hw, CK_16XX),
|
||||
CLK("omap-mcbsp.1", "ick", &dummy_ck.hw, CK_1510 | CK_310),
|
||||
CLK("omap-mcbsp.2", "ick", &armper_ck.clk.hw, CK_16XX),
|
||||
CLK("omap-mcbsp.2", "ick", &dummy_ck.hw, CK_1510 | CK_310),
|
||||
CLK("omap-mcbsp.3", "ick", &dspper_ck.hw, CK_16XX),
|
||||
CLK("omap-mcbsp.3", "ick", &dummy_ck.hw, CK_1510 | CK_310),
|
||||
CLK("omap-mcbsp.1", "fck", &dspxor_ck.hw, CK_16XX | CK_1510 | CK_310),
|
||||
CLK("omap-mcbsp.2", "fck", &armper_ck.clk.hw, CK_16XX | CK_1510 | CK_310),
|
||||
CLK("omap-mcbsp.3", "fck", &dspxor_ck.hw, CK_16XX | CK_1510 | CK_310),
|
||||
};
|
||||
|
||||
/*
|
||||
|
|
@ -778,9 +713,6 @@ int __init omap1_clk_init(void)
|
|||
/* By default all idlect1 clocks are allowed to idle */
|
||||
arm_idlect1_mask = ~0;
|
||||
|
||||
for (c = omap_clks; c < omap_clks + ARRAY_SIZE(omap_clks); c++)
|
||||
clk_preinit(c->lk.clk);
|
||||
|
||||
cpu_mask = 0;
|
||||
if (cpu_is_omap1710())
|
||||
cpu_mask |= CK_1710;
|
||||
|
|
@ -793,16 +725,10 @@ int __init omap1_clk_init(void)
|
|||
if (cpu_is_omap310())
|
||||
cpu_mask |= CK_310;
|
||||
|
||||
for (c = omap_clks; c < omap_clks + ARRAY_SIZE(omap_clks); c++)
|
||||
if (c->cpu & cpu_mask) {
|
||||
clkdev_add(&c->lk);
|
||||
clk_register(c->lk.clk);
|
||||
}
|
||||
|
||||
/* Pointers to these clocks are needed by code in clock.c */
|
||||
api_ck_p = clk_get(NULL, "api_ck");
|
||||
ck_dpll1_p = clk_get(NULL, "ck_dpll1");
|
||||
ck_ref_p = clk_get(NULL, "ck_ref");
|
||||
api_ck_p = &api_ck.clk;
|
||||
ck_dpll1_p = &ck_dpll1;
|
||||
ck_ref_p = &ck_ref;
|
||||
|
||||
if (cpu_is_omap7xx())
|
||||
ck_ref.rate = 13000000;
|
||||
|
|
@ -844,10 +770,7 @@ int __init omap1_clk_init(void)
|
|||
}
|
||||
}
|
||||
}
|
||||
propagate_rate(&ck_dpll1);
|
||||
/* Cache rates for clocks connected to ck_ref (not dpll1) */
|
||||
propagate_rate(&ck_ref);
|
||||
omap1_show_rates();
|
||||
|
||||
if (machine_is_omap_perseus2() || machine_is_omap_fsample()) {
|
||||
/* Select slicer output as OMAP input clock */
|
||||
omap_writew(omap_readw(OMAP7XX_PCC_UPLD_CTRL) & ~0x1,
|
||||
|
|
@ -879,16 +802,28 @@ int __init omap1_clk_init(void)
|
|||
*/
|
||||
omap_writew(0x0000, ARM_IDLECT2); /* Turn LCD clock off also */
|
||||
|
||||
/*
|
||||
* Only enable those clocks we will need, let the drivers
|
||||
* enable other clocks as necessary
|
||||
*/
|
||||
clk_enable(&armper_ck.clk);
|
||||
clk_enable(&armxor_ck.clk);
|
||||
clk_enable(&armtim_ck.clk); /* This should be done by timer code */
|
||||
for (c = omap_clks; c < omap_clks + ARRAY_SIZE(omap_clks); c++) {
|
||||
if (!(c->cpu & cpu_mask))
|
||||
continue;
|
||||
|
||||
if (cpu_is_omap15xx())
|
||||
clk_enable(&arm_gpio_ck);
|
||||
if (c->lk.clk_hw->init) { /* NULL if provider already registered */
|
||||
const struct clk_init_data *init = c->lk.clk_hw->init;
|
||||
const char *name = c->lk.clk_hw->init->name;
|
||||
int err;
|
||||
|
||||
err = clk_hw_register(NULL, c->lk.clk_hw);
|
||||
if (err < 0) {
|
||||
pr_err("failed to register clock \"%s\"! (%d)\n", name, err);
|
||||
/* may be tried again, restore init data */
|
||||
c->lk.clk_hw->init = init;
|
||||
continue;
|
||||
}
|
||||
}
|
||||
|
||||
clk_hw_register_clkdev(c->lk.clk_hw, c->lk.con_id, c->lk.dev_id);
|
||||
}
|
||||
|
||||
omap1_show_rates();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -900,7 +835,7 @@ void __init omap1_clk_late_init(void)
|
|||
unsigned long rate = ck_dpll1.rate;
|
||||
|
||||
/* Find the highest supported frequency and enable it */
|
||||
if (omap1_select_table_rate(&virtual_ck_mpu, ~0)) {
|
||||
if (omap1_select_table_rate(&virtual_ck_mpu, ~0, arm_ck.rate)) {
|
||||
pr_err("System frequencies not set, using default. Check your config.\n");
|
||||
/*
|
||||
* Reprogramming the DPLL is tricky, it must be done from SRAM.
|
||||
|
|
|
|||
|
|
@ -64,7 +64,7 @@ static inline u32 omap_cs3_phys(void)
|
|||
#define OMAP1_IO_OFFSET 0x00f00000 /* Virtual IO = 0xff0b0000 */
|
||||
#define OMAP1_IO_ADDRESS(pa) IOMEM((pa) - OMAP1_IO_OFFSET)
|
||||
|
||||
#include <mach/serial.h>
|
||||
#include "serial.h"
|
||||
|
||||
/*
|
||||
* ---------------------------------------------------------------------------
|
||||
|
|
|
|||
|
|
@ -1,117 +0,0 @@
|
|||
/*
|
||||
* arch/arm/plat-omap/include/mach/uncompress.h
|
||||
*
|
||||
* Serial port stubs for kernel decompress status messages
|
||||
*
|
||||
* Initially based on:
|
||||
* linux-2.4.15-rmk1-dsplinux1.6/arch/arm/plat-omap/include/mach1510/uncompress.h
|
||||
* Copyright (C) 2000 RidgeRun, Inc.
|
||||
* Author: Greg Lonnon <glonnon@ridgerun.com>
|
||||
*
|
||||
* Rewritten by:
|
||||
* Author: <source@mvista.com>
|
||||
* 2004 (c) MontaVista Software, Inc.
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public License
|
||||
* version 2. This program is licensed "as is" without any warranty of any
|
||||
* kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#include <linux/types.h>
|
||||
#include <linux/serial_reg.h>
|
||||
|
||||
#include <asm/memory.h>
|
||||
#include <asm/mach-types.h>
|
||||
|
||||
#include "serial.h"
|
||||
|
||||
#define MDR1_MODE_MASK 0x07
|
||||
|
||||
volatile u8 *uart_base;
|
||||
int uart_shift;
|
||||
|
||||
/*
|
||||
* Store the DEBUG_LL uart number into memory.
|
||||
* See also debug-macro.S, and serial.c for related code.
|
||||
*/
|
||||
static void set_omap_uart_info(unsigned char port)
|
||||
{
|
||||
/*
|
||||
* Get address of some.bss variable and round it down
|
||||
* a la CONFIG_AUTO_ZRELADDR.
|
||||
*/
|
||||
u32 ram_start = (u32)&uart_shift & 0xf8000000;
|
||||
u32 *uart_info = (u32 *)(ram_start + OMAP_UART_INFO_OFS);
|
||||
*uart_info = port;
|
||||
}
|
||||
|
||||
static inline void putc(int c)
|
||||
{
|
||||
if (!uart_base)
|
||||
return;
|
||||
|
||||
/* Check for UART 16x mode */
|
||||
if ((uart_base[UART_OMAP_MDR1 << uart_shift] & MDR1_MODE_MASK) != 0)
|
||||
return;
|
||||
|
||||
while (!(uart_base[UART_LSR << uart_shift] & UART_LSR_THRE))
|
||||
barrier();
|
||||
uart_base[UART_TX << uart_shift] = c;
|
||||
}
|
||||
|
||||
static inline void flush(void)
|
||||
{
|
||||
}
|
||||
|
||||
/*
|
||||
* Macros to configure UART1 and debug UART
|
||||
*/
|
||||
#define _DEBUG_LL_ENTRY(mach, dbg_uart, dbg_shft, dbg_id) \
|
||||
if (machine_is_##mach()) { \
|
||||
uart_base = (volatile u8 *)(dbg_uart); \
|
||||
uart_shift = (dbg_shft); \
|
||||
port = (dbg_id); \
|
||||
set_omap_uart_info(port); \
|
||||
break; \
|
||||
}
|
||||
|
||||
#define DEBUG_LL_OMAP7XX(p, mach) \
|
||||
_DEBUG_LL_ENTRY(mach, OMAP1_UART##p##_BASE, OMAP7XX_PORT_SHIFT, \
|
||||
OMAP1UART##p)
|
||||
|
||||
#define DEBUG_LL_OMAP1(p, mach) \
|
||||
_DEBUG_LL_ENTRY(mach, OMAP1_UART##p##_BASE, OMAP_PORT_SHIFT, \
|
||||
OMAP1UART##p)
|
||||
|
||||
static inline void arch_decomp_setup(void)
|
||||
{
|
||||
int port = 0;
|
||||
|
||||
/*
|
||||
* Initialize the port based on the machine ID from the bootloader.
|
||||
* Note that we're using macros here instead of switch statement
|
||||
* as machine_is functions are optimized out for the boards that
|
||||
* are not selected.
|
||||
*/
|
||||
do {
|
||||
/* omap7xx/8xx based boards using UART1 with shift 0 */
|
||||
DEBUG_LL_OMAP7XX(1, herald);
|
||||
DEBUG_LL_OMAP7XX(1, omap_perseus2);
|
||||
|
||||
/* omap15xx/16xx based boards using UART1 */
|
||||
DEBUG_LL_OMAP1(1, ams_delta);
|
||||
DEBUG_LL_OMAP1(1, nokia770);
|
||||
DEBUG_LL_OMAP1(1, omap_h2);
|
||||
DEBUG_LL_OMAP1(1, omap_h3);
|
||||
DEBUG_LL_OMAP1(1, omap_innovator);
|
||||
DEBUG_LL_OMAP1(1, omap_osk);
|
||||
DEBUG_LL_OMAP1(1, omap_palmte);
|
||||
DEBUG_LL_OMAP1(1, omap_palmz71);
|
||||
|
||||
/* omap15xx/16xx based boards using UART2 */
|
||||
DEBUG_LL_OMAP1(2, omap_palmtt);
|
||||
|
||||
/* omap15xx/16xx based boards using UART3 */
|
||||
DEBUG_LL_OMAP1(3, sx1);
|
||||
} while (0);
|
||||
}
|
||||
|
|
@ -15,10 +15,8 @@
|
|||
#include <asm/mach/map.h>
|
||||
|
||||
#include "tc.h"
|
||||
#include "mux.h"
|
||||
#include "iomap.h"
|
||||
#include "common.h"
|
||||
#include "clock.h"
|
||||
|
||||
/*
|
||||
* The machine specific code may provide the extra mapping besides the
|
||||
|
|
@ -125,11 +123,6 @@ void __init omap1_init_early(void)
|
|||
*/
|
||||
omap_writew(0x0, MPU_PUBLIC_TIPB_CNTL);
|
||||
omap_writew(0x0, MPU_PRIVATE_TIPB_CNTL);
|
||||
|
||||
/* Must init clocks early to assure that timer interrupt works
|
||||
*/
|
||||
omap1_clk_init();
|
||||
omap1_mux_init();
|
||||
}
|
||||
|
||||
void __init omap1_init_late(void)
|
||||
|
|
|
|||
|
|
@ -19,8 +19,7 @@
|
|||
|
||||
#include <asm/mach-types.h>
|
||||
|
||||
#include <mach/serial.h>
|
||||
|
||||
#include "serial.h"
|
||||
#include "mux.h"
|
||||
#include "pm.h"
|
||||
#include "soc.h"
|
||||
|
|
|
|||
|
|
@ -51,8 +51,10 @@
|
|||
#include <asm/mach/time.h>
|
||||
|
||||
#include "hardware.h"
|
||||
#include "mux.h"
|
||||
#include "iomap.h"
|
||||
#include "common.h"
|
||||
#include "clock.h"
|
||||
|
||||
#ifdef CONFIG_OMAP_MPU_TIMER
|
||||
|
||||
|
|
@ -224,6 +226,9 @@ static inline void omap_mpu_timer_init(void)
|
|||
*/
|
||||
void __init omap1_timer_init(void)
|
||||
{
|
||||
omap1_clk_init();
|
||||
omap1_mux_init();
|
||||
|
||||
if (omap_32k_timer_init() != 0)
|
||||
omap_mpu_timer_init();
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue