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net: dsa: bcm_sf2: implement GPHY power down
Implement the power on/off recommended procedure for the Single GPHY we have on our Starfighter 2 switch. In order to make sure we get proper LED link/activity signaling during suspend, switch the link indication from the Switch/MAC to the PHY. Finally, since the GPHY needs to be reset to be put in low power mode, we will loose any context applied to it: workarounds, EEE etc.. so we need to call phy_init_hw() to get our fixups re-applied successfully. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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parent
b083668c93
commit
9af197a8f6
2 changed files with 46 additions and 10 deletions
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@ -238,17 +238,28 @@ static void bcm_sf2_gphy_enable_set(struct dsa_switch *ds, bool enable)
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struct bcm_sf2_priv *priv = ds_to_priv(ds);
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u32 reg;
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if (!enable)
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return;
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reg = reg_readl(priv, REG_SPHY_CNTRL);
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if (enable) {
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reg |= PHY_RESET;
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reg &= ~(EXT_PWR_DOWN | IDDQ_BIAS | CK25_DIS);
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reg_writel(priv, reg, REG_SPHY_CNTRL);
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udelay(21);
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reg = reg_readl(priv, REG_SPHY_CNTRL);
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reg &= ~PHY_RESET;
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} else {
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reg |= EXT_PWR_DOWN | IDDQ_BIAS | PHY_RESET;
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reg_writel(priv, reg, REG_SPHY_CNTRL);
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mdelay(1);
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reg |= CK25_DIS;
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}
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reg_writel(priv, reg, REG_SPHY_CNTRL);
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reg = reg_readl(priv, REG_SPHY_CNTRL);
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reg |= PHY_RESET;
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reg &= ~(EXT_PWR_DOWN | IDDQ_BIAS);
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reg_writel(priv, reg, REG_SPHY_CNTRL);
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udelay(21);
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reg = reg_readl(priv, REG_SPHY_CNTRL);
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reg &= ~PHY_RESET;
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reg_writel(priv, reg, REG_SPHY_CNTRL);
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/* Use PHY-driven LED signaling */
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if (!enable) {
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reg = reg_readl(priv, REG_LED_CNTRL(0));
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reg |= SPDLNK_SRC_SEL;
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reg_writel(priv, reg, REG_LED_CNTRL(0));
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}
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}
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static int bcm_sf2_port_setup(struct dsa_switch *ds, int port,
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@ -266,6 +277,24 @@ static int bcm_sf2_port_setup(struct dsa_switch *ds, int port,
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/* Clear the Rx and Tx disable bits and set to no spanning tree */
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core_writel(priv, 0, CORE_G_PCTL_PORT(port));
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/* Re-enable the GPHY and re-apply workarounds */
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if (port == 0 && priv->hw_params.num_gphy == 1) {
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bcm_sf2_gphy_enable_set(ds, true);
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if (phy) {
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/* if phy_stop() has been called before, phy
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* will be in halted state, and phy_start()
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* will call resume.
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*
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* the resume path does not configure back
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* autoneg settings, and since we hard reset
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* the phy manually here, we need to reset the
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* state machine also.
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*/
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phy->state = PHY_READY;
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phy_init_hw(phy);
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}
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}
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/* Enable port 7 interrupts to get notified */
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if (port == 7)
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intrl2_1_mask_clear(priv, P_IRQ_MASK(P7_IRQ_OFF));
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@ -299,6 +328,9 @@ static void bcm_sf2_port_disable(struct dsa_switch *ds, int port,
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intrl2_1_writel(priv, P_IRQ_MASK(P7_IRQ_OFF), INTRL2_CPU_CLEAR);
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}
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if (port == 0 && priv->hw_params.num_gphy == 1)
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bcm_sf2_gphy_enable_set(ds, false);
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if (dsa_is_cpu_port(ds, port))
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off = CORE_IMP_CTL;
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else
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@ -61,6 +61,10 @@
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#define LPI_COUNT_SHIFT 9
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#define LPI_COUNT_MASK 0x3F
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#define REG_LED_CNTRL_BASE 0x90
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#define REG_LED_CNTRL(x) (REG_LED_CNTRL_BASE + (x) * 4)
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#define SPDLNK_SRC_SEL (1 << 24)
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/* Register set relative to 'INTRL2_0' and 'INTRL2_1' */
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#define INTRL2_CPU_STATUS 0x00
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#define INTRL2_CPU_SET 0x04
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