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dt-bindings: riscv: Fix CPU schema errors
Fix the errors in the RiscV CPU DT schema:
Documentation/devicetree/bindings/riscv/cpus.example.dt.yaml: cpu@0: 'timebase-frequency' is a required property
Documentation/devicetree/bindings/riscv/cpus.example.dt.yaml: cpu@1: 'timebase-frequency' is a required property
Documentation/devicetree/bindings/riscv/cpus.example.dt.yaml: cpu@0: compatible:0: 'riscv' is not one of ['sifive,rocket0', 'sifive,e5', 'sifive,e51', 'sifive,u54-mc', 'sifive,u54', 'sifive,u5']
Documentation/devicetree/bindings/riscv/cpus.example.dt.yaml: cpu@0: compatible: ['riscv'] is too short
Documentation/devicetree/bindings/riscv/cpus.example.dt.yaml: cpu@0: 'timebase-frequency' is a required property
The DT spec allows for 'timebase-frequency' to be in 'cpu' or 'cpus' node
and RiscV requires it in /cpus node, so make it disallowed in cpu
nodes.
Fixes: 4fd669a8c4
("dt-bindings: riscv: convert cpu binding to json-schema")
Cc: Palmer Dabbelt <palmer@sifive.com>
Cc: Albert Ou <aou@eecs.berkeley.edu>
Cc: linux-riscv@lists.infradead.org
Acked-by: Paul Walmsley <paul.walmsley@sifive.com>
Signed-off-by: Rob Herring <robh@kernel.org>
This commit is contained in:
parent
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commit
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1 changed files with 13 additions and 16 deletions
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@ -24,15 +24,17 @@ description: |
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properties:
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compatible:
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items:
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- enum:
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- sifive,rocket0
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- sifive,e5
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- sifive,e51
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- sifive,u54-mc
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- sifive,u54
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- sifive,u5
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- const: riscv
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oneOf:
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- items:
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- enum:
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- sifive,rocket0
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- sifive,e5
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- sifive,e51
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- sifive,u54-mc
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- sifive,u54
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- sifive,u5
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- const: riscv
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- const: riscv # Simulator only
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description:
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Identifies that the hart uses the RISC-V instruction set
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and identifies the type of the hart.
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@ -66,12 +68,8 @@ properties:
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insensitive, letters in the riscv,isa string must be all
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lowercase to simplify parsing.
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timebase-frequency:
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type: integer
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minimum: 1
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description:
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Specifies the clock frequency of the system timer in Hz.
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This value is common to all harts on a single system image.
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# RISC-V requires 'timebase-frequency' in /cpus, so disallow it here
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timebase-frequency: false
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interrupt-controller:
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type: object
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@ -93,7 +91,6 @@ properties:
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required:
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- riscv,isa
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- timebase-frequency
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- interrupt-controller
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examples:
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